Compensating Detection Latency of FPGA Scrubbers with a Collaborative Functional Hardware Duplication

We investigate the implementation of triple modular redundancy (TMR) with different number of voters in a softcore RISC-V microprocessor to mitigate radiation-induced faults in the configuration memory (CRAM) of SRAM-based FPGA. The case-study microprocessor is the Steel Core implemented in AMD Xilinx 7-Series/Zynq-7000 device, executing benchmark software on the FreeRTOS operating system. We implemented coarse-grained TMR (CGTMR) and fine-grained distributed TMR (FGDTMR) using an automated redundancy and voter insertion tool. TMR is used in combination with memory scrubber featured by the FPGA hardware, which uses error correction codes (ECC) to revert radiation-induced faults in CRAM. Fault injection in CRAM emulating radiation-induced faults is used to evaluate the benefits of both TMR and ECC. Under fault injection, combining the fault masking capability of TMR with the self-healing by ECC, improved mean time between failures (MTBF) up to 5×. ECC alone did not improve significantly the fault tolerance. Without ECC, FGDTMR improves MTBF in 2×, but at a higher cost in circuit area and resources usage. When combined with ECC, the CGTMR provides fault tolerance comparable to FGDTMR but with 30% less resources usage.

Field-programmable gate arrays are susceptible to radiation-induced single event upsets. These are commonly dealt with using triple modular redundancy (TMR) and module-based configuration memory error recovery (MER). By triplicating components and voting on their outputs, TMR helps localise configuration memory errors, and by reconfiguring faulty components, MER swiftly corrects them. However, the order in which TMR voters are checked inevitably impacts the overall system reliability. In this study, the authors outline an approach for computing the reliability of TMR–MER systems that consist of finitely many components. They demonstrate that system reliability is improved when the more vulnerable components are checked more frequently than when they are checked in round-robin order. They propose a genetic algorithm for finding a voter checking schedule that maximises the reliability of TMR–MER systems. Results indicate that the mean time to failure (MTTF) of these systems can be increased by up to 400% when variable-rate voter checking (VRVC) is used instead of round robin. They show that VRVC achieves 15–23% increase in MTTF with a 10× reduction in checking frequency to reduce system power. They also found that VRVC detects errors 44% faster on average than round robin.

In this work we present a novel fault-tolerant circuits design method. It combines time and area redundancy to achieve error-correction abilities similar to a triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing a complete stuck-at fault testability will be presented. Our method allows to test combinational parts of the circuit using a universal short-duration offline test. The offline-testable module with an online-checker allows to compose a fault-tolerant system with the mentioned properties. This system will be denoted as a time-extended duplex scheme. In this scheme the offline test is sufficiently short to allow error correction during the computation (paused pipeline). The presented method adopts some principles from dual-rail logic and asynchronous circuits design.

Soft errors in General Purpose Graphics Processing Units (GPGPUs) result in data or control flow errors. Error detection and correction methods for data and control flow errors are orthogonal, and these methods incur separate area, power, and performance overheads. This paper proposes a low-overhead predictive control flow error detection method called GPGPU Predictive Detector (GPD), which leverages data flow error detection and correction methods to detect control flow errors. GPD is non-intrusive to application software and transparent to users. GPD is built on earlier work on data flow error detection and correction methods DDSR and TREFU. In GPD, DDSR and TREFU combined architecture protects all non-control flow instructions. The control flow error is detected by calculating the address of the instruction that succeeds the control flow instruction in advance and comparing it with the actual address it accesses. The effectiveness of GPD has been shown through a set of ISPASS-2009 and RODINIA benchmarks. Relative to a non-fault-tolerant GPGPU architecture, GPD has a performance overhead of 5% and average and peak power overheads of 4% and 3%, respectively. We prove through induction that the GPD provides fault coverage against GPGPU control flow and data flow errors.

This paper presents the architecture of the Safety Programmable Logic Controller (SPLC) for advanced nuclear safety systems and describes the evaluation and analyses of reliability for the SPLC using the Markov model. The SPLC is designed to have structural flexibility for users to select module redundancy according to the requirements of specific applications. To be used for the nuclear safety system, the SPLC is configured for multiple modular redundancy composed of dual modular redundancy and triple modular redundancy. Markov models were developed for three types of existing safety-grade Programmable Logic Controller (PLC) architectures and the SPLC, and the reliabilities of the architectures were then evaluated and analyzed using the models. The results show that the reliability of SPLC is up to 1.6 times better than those of the three PLC architectures, and the mean time to failure (MTTF) of the SPLC is up to 22 000 h better than those of the three. From the reliability analyses, the failure rate of each module in the SPLC should be <2 × 10−4/h, and the MTTF average increase rate depending on the fault coverage factor (FCF) increment, i.e., ΔMTFF/ΔFCF, is 4 months/0.1.

Urban buildings use a large amount of electrical energy every day, especially for cooling. One common reason Fault tolerance is a critical requirement in safety-critical and high-reliability digital systems such as aerospace electronics, medical devices, industrial automation, and communication infrastructure. This project focuses on the design and development of a fault-tolerant digital system using the Triple Modular Redundancy (TMR) technique [1], [3]. In a TMR architecture, three identical modules execute the same operation in parallel, and a majority voting mechanism determines the correct output even if one module fails due to transient faults, permanent hardware failures, or radiation-induced errors [1]. The proposed system implements replication at the hardware level and incorporates a robust majority voter circuit to ensure continuous operation without performance degradation [2], [3]. The design is simulated and validated using digital design tools to analyze system behavior under fault-injection scenarios. Performance metrics such as reliability, error-masking capability, propagation delay, and resource utilization are examined to evaluate the effectiveness of the TMR approach. The results demonstrate that TMR significantly enhances system reliability and resilience by masking single-point failures, making it a practical solution for mission-critical applications where system downtime or incorrect outputs are unacceptable [1], [3]. This project provides a comprehensive understanding of fault-tolerant design strategies and highlights the trade-offs between hardware redundancy, system complexity, and operational reliability.

The solution of large eigenproblems is involved in many scientific and engineering applications when for instance, stability analysis is a concern. For large simulation in material physics or thermo-acoustics, the calculation can last for many hours on large parallel platforms. On future large-scale systems, the mean time between failures (MTBF) of the system is expected to decrease so that many faults could occur during the solution of large eigenproblems. Consequently, it becomes critical to design parallel eigensolvers that can survive faults. In that framework, we investigate the relevance of approaches relying on numerical techniques, which might be combined with more classical techniques for real large-scale parallel implementations. Because we focus on numerical remedies we do not consider parallel implementations nor parallel experiments but only numerical experiments. We assume that a separate mechanism ensures the fault detection and that a system layer provides support for setting back the environment (processes,. . .) in a running state. Once the system is in a running state, after a fault, our main objective is to provide robust resilient schemes so that the eigensolver may keep converging in the presence of the fault without restarting the calculation from scratch. For this purpose, we extend the interpolation-restart (IR) strategies initially introduced for the solution of linear systems in a previous work to the solution of eigenproblems in this paper. For a given numerical scheme, the IR strategies consist of extracting relevant spectral information from available data after a fault. After data extraction, a well-selected part of the missing data is regenerated through interpolation strategies to constitute a meaningful input to restart the numerical algorithm. One of the main features of this numerical remedy is that it does not require extra resources, i.e., computational unit or computing time, when no fault occurs. In this paper, we revisit a few state-of-the-art methods for solving large sparse eigenvalue problems namely the Arnoldi methods, subspace iteration methods and the Jacobi-Davidson method, in the light of our IR strategies. For each considered eigensolver, we adapt the IR strategies to regenerate as much spectral information as possible. Through extensive numerical experiments, we study the respective robustness of the resulting resilient schemes with respect to the MTBF and to the amount of data loss via qualitative and quantitative illustrations. 1. Introduction. The computation of eigenpairs (eigenvalues and eigenvectors) of large sparse matrices is involved in many scientific and engineering applications such as when stability analysis is a concern. To name a few, it appears in structural dynamics, thermodynamics, thermo-acoustics, quantum chemistry. With the permanent increase of the computational power of high performance computing (HPC) systems by using a larger and larger number of CPU cores or specialized processing units, HPC applications are increasingly prone to faults. To guarantee fault tolerance, two classes of strategies are required. One for the fault detection and the other for fault correction. Faults such as computational node crashes are obvious to detect while silent faults may be challenging to detect. To cope with silent faults, a duplication strategy is commonly used for fault detection [18, 39] by comparing the outputs, while triple modular redundancy (TMR) is used for fault detection and correction [34, 37]. However, the additional computational resources required by such replication strategies may represent a severe penalty. Instead of replicating computational resources, studies [7, 36] propose a time redundancy model for fault detection. It consists in repeating computation twice on the same resource. The advantage of time redundancy models is the flexibility at application level; software developers can indeed select only a set of critical instructions to protect. Recomputing only some instructions instead of the whole application lowers the time redundancy overhead [25]. In some numerical simulations, data naturally satisfy well defined mathematical properties. These properties can be efficiently exploited for fault detection through a periodical check of the numerical properties during computation [10]. Checkpoint/restart is the most studied fault recovery strategy in the context of HPC systems. The common checkpoint/restart scheme consists in periodically saving data onto a reliable storage device such as a remote disk. When a fault occurs, a rollback is performed to the point of the most recent and consistent checkpoint. According to the implemented checkpoint strategy, all processes

In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.

The time difference method based ultra-high-frequency (UHF) partial discharge (PD) localization has not been extensively applied in substations due to its excessive localization error. A novel and effective PD localization error correction method, consisting of two multiple radial basis function (RBF) networks, RBF t for time delay error correction and RBF p for PD position error correction, is reported in this paper as a solution. Furthermore, the RBF t , trained by time delay value measured in field experiments and RBF p , trained by the localization results corrected by RBF t , have both adopted the multiple neural networks structure which could further improve their error correction ability. The field tests proved that, the error correction networks RBF t and RBF p have strong ability to learn and simulate the error distribution. After the error correction and compensation, the PD distance localization error is reduced from 3m to 0.5m and the direction angle error is reduced from 12° to less than 5°. Universality experiments also revealed that the proposed method has a good adaptability for different time-delay algorithms and different types of PD models, which proved the robustness and effectiveness of proposed method.

We consider methods of error detection and/or error correction in software and hardware of a distributed system computing values of numerical functions. These methods are based on software and hardware redundancy for the computation of additional check functions. The check functions are easily derived for any given multiplicity of errors. The redundancy does not depend on the number of processors in the original system and depends only on the multiplicity of errors. We describe methods for the construction of optimal checks, required software and hardware redundancy, and implementation of the corresponding error detecting/correcting procedures by a distributed system.

Next Generation Sequencing (NGS) technologies produce large quantities of short length reads with higher error rates. Erroneous reads that cannot be aligned, are either ignored during de-novo sequencing, or must be suitably corrected. Such reads pose problems for mapping as well, since it is difficult to distinguish errors from true variants. Methods for detection and correction of errors typically rely on frequencies of substrings of the reads. Suffix trees are often utilized for this purpose, since they can be used to index and count the frequencies of substrings of all lengths. Existing suffix-tree based methods detect errors by identifying statistically under-represented branches (suffixes) and fix them. However, they do not refer back to the reads to put the correction in context. Since an error in a single read manifests itself at multiple nodes of a suffix tree, a read-driven approach that relies on its multiple manifestations is expected to perform better. Based on this observation, we develop an algorithm, PLURIBUS, which reconciles corrections suggested by multiple manifestations of an error using a voting scheme. We compare the accuracy of PLURIBUS in detecting and correcting errors against existing error correction techniques using simulated sequencing data. We also assess the impact of error correction on the performance of sequence assembly. Our results show that PLURIBUS corrects errors with improved precision and enables the assembler to generate longer contigs, particularly when the genome is longer, or coverage is lower. PLURIBUS is freely available at http://compbio.case.edu/pluribus/.

The fault‐tolerant technique has been frequently employed to realize a highly reliable computer system. This paper considers the Triple‐Modular Redundancy (TMR) system, which is one of the fault‐tolerant systems whereby the system is partitioned into several blocks and the majority decision is made in each block. The reliability of such a system is evaluated. Based on the relation between the number of partitions and the failure rate of such a system, the following two types of models are assumed:(1) TMR network model, where the failure rate of the whole system increases with the number of partitions, when the failure rate of the block is kept constant.(2) LSI model, where the block failure rate decreases with the number of partitions, when the failure rate of the whole system is kept constant. Especially, in the model (2), the pin‐gate ratio of LSI is taken into consideration. For these models, the expression for the Mean‐Time‐To‐Failure (MTTF), which is the mean operation time until a system failure occurs, is derived. The general tendency of MTTF is analyzed. By numerical examples, the improvement of MTTF by partitioning is demonstrated. The improvement of the TMR system by partitioning is demonstrated quantitatively.

Space computing systems commonly use field-programmable gate arrays to provide fault tolerance by applying triple modular redundancy (TMR) to existing register-transfer-level (RTL) code. Although effective, this approach has a 3× area overhead that can be prohibitive for many designs that often allocate resources before considering effects of redundancy. Although a designer could modify existing RTL code to reduce resource usage, such a process is time consuming and error prone. Integrating redundancy into high-level synthesis is a more attractive approach that enables synthesis to rapidly explore different tradeoffs at no cost to the designer. In this paper, we introduce a scheduling and binding heuristic for high-level synthesis that explores tradeoffs between resource usage, latency, and the amount of redundancy. In many cases, an application will not require 100% error correction, which enables significant flexibility for scheduling and binding to reduce resources. Even for applications that require 100% error correction, our heuristic is able to explore solutions that sacrifice latency for reduced resources, and typically save up to 47% when relaxing the latency up to 2×. When the error constraint is reduced to 70%, our heuristic achieves typical resource savings ranging from 18% to 49% when relaxing the latency up to 2×, with a maximum of 77%. Even when comparing with optimized RTL designs, our heuristic uses up to 61% fewer resources than TMR.

Offset, gain and time mismatch errors exist in the channels of the time-interleaved analog-to-digital converter (TIADC), which severely affect the signal-to-noise and distortion ratio (SNDR), spurious-free dynamic range (SFDR) and effective number of bits (ENOB). Here, an error detection and correction method of TIADC based on genetic algorithm (GA) optimization is presented. The algorithm based on sine fitting is used for the first estimation and rough correction of the input signal, and GA is used for the second detection and fine correction of channel mismatch errors on the signal after frequency domain filtering. Experimental results show that the SNDR of the TIADC system is enhanced to 92.24 dB, the SFDR is enhanced to 102.05 dB, the ENOB is enhanced to 15.03 bits and the spectrum spurs are reduced. This method provides a new idea for error detection and correction of high-resolution TIADC systems with more than 16 bits.

With the development of satellite communications, on-board processing (OBP) obtains more and more attentions due to the increased efficiency and performance. However, the large amounts of digital circuits in the OBP transponders are sensitive to the high-energy particles in space radiation environments, which may cause various kinds of single event effect. Among these effects, single event upset (SEU) is the major potential reason for the instability of the satellite communication systems. Triple modular redundancy (TMR) is a classical and effective method for mitigating the SEU in digital circuits. However, since three identical logic modules and a voting circuit are needed in TMR, the overhead is so high that the scheme may not be applicable on the on-board digital processing platform with very limited area and power resources. Therefore, how to design a more cost-effective fault-tolerant method becomes a critical issue. Considering that FIR-like processing is frequently used on OBP platform, in this article, a dual modules (DM) plus checking module based on residue code (DM-CRC) architecture for SEU-tolerant FIR design is proposed. Although this architecture reduces the area overhead dramatically, we find that the fault missing rate is still high if single-sample checking (SSC) is used. To solve this problem, a Multi-sample checking DM-CRC (MSC-DM-CRC) is further proposed. Our analysis shows that the MSC-DM-CRC scheme can make the fault missing rate small enough without reducing the actual throughput. By simulations it is shown that, when the modulus for CRC is 7 and the number of samples for MSC is 4, the reduction of area overhead relative to TMR is over 20% and the fault missing rate is as low as 0.05%.