Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy

Soft errors in General Purpose Graphics Processing Units (GPGPUs) result in data or control flow errors. Error detection and correction methods for data and control flow errors are orthogonal, and these methods incur separate area, power, and performance overheads. This paper proposes a low-overhead predictive control flow error detection method called GPGPU Predictive Detector (GPD), which leverages data flow error detection and correction methods to detect control flow errors. GPD is non-intrusive to application software and transparent to users. GPD is built on earlier work on data flow error detection and correction methods DDSR and TREFU. In GPD, DDSR and TREFU combined architecture protects all non-control flow instructions. The control flow error is detected by calculating the address of the instruction that succeeds the control flow instruction in advance and comparing it with the actual address it accesses. The effectiveness of GPD has been shown through a set of ISPASS-2009 and RODINIA benchmarks. Relative to a non-fault-tolerant GPGPU architecture, GPD has a performance overhead of 5% and average and peak power overheads of 4% and 3%, respectively. We prove through induction that the GPD provides fault coverage against GPGPU control flow and data flow errors.

Error detection and correction which has been used in communication and memory design is becoming increasingly important in fault tolerant logic circuit design. As a result of the aggressive technology scaling, the current high-density integrated circuits are easily succumbed to faulty operations generated from many sources including stuck-at-faults, radiation induced faults, or malicious eavesdropper attacks. The currently used techniques like low-density parity-check (LDPC) and Hamming code based fault masking to mitigate bit flips in the digital circuits are either single bit error correcting or multiple error correctable with Bose-Choudhury-Hocquenghem (BCH) and Reed-solomon based methods with very large overheads. This paper introduce a novel cross code based method that can correct multiple errors with minimal compromise in error correction capability and area. The key idea of the novel method proposed in this paper is that do not correct all the errors but minimize their probability being escaped. Experimental results of the proposed methods show that the following: (1) area overhead is 101% for Hamming cross code and 106% for BCH cross code for a 90-bit finite field multiplier and (2) 150% for Hamming cross code and 170% for BCH cross codes for practically used 163-bit digit serial polynomial basis multiplier. Thus, the proposed methods are significantly efficient compared to Triple Modular Redundancy (TMR), LDPC, Hamming based methods in terms of area overhead and also the first attempted approach to a low complexity multiple error correctable digit serial multiplier to the best of the authors knowledge.

Scrubbing is an effective FPGA error detection and correction method for configuration memoryâǍŹs faults. Scrubbing, however, is a serial procedure with several milliseconds latency. This latency may allow some errors to affect the system functionality. To prevent this effect, we have devised our duplication method of reliability operating in parallel and hand-in-hand with scrubbing to recover from errors. Our experiments results demonstrate that mean time to failure (MTTF) is improved by 966% and 150% over the pure scrubbing and triple modular redundancy (TMR), respectively. Additionally, our method enters the safe fail procedure in the remaining cases.

We consider methods of error detection and/or error correction in software and hardware of a distributed system computing values of numerical functions. These methods are based on software and hardware redundancy for the computation of additional check functions. The check functions are easily derived for any given multiplicity of errors. The redundancy does not depend on the number of processors in the original system and depends only on the multiplicity of errors. We describe methods for the construction of optimal checks, required software and hardware redundancy, and implementation of the corresponding error detecting/correcting procedures by a distributed system.

Next Generation Sequencing (NGS) technologies produce large quantities of short length reads with higher error rates. Erroneous reads that cannot be aligned, are either ignored during de-novo sequencing, or must be suitably corrected. Such reads pose problems for mapping as well, since it is difficult to distinguish errors from true variants. Methods for detection and correction of errors typically rely on frequencies of substrings of the reads. Suffix trees are often utilized for this purpose, since they can be used to index and count the frequencies of substrings of all lengths. Existing suffix-tree based methods detect errors by identifying statistically under-represented branches (suffixes) and fix them. However, they do not refer back to the reads to put the correction in context. Since an error in a single read manifests itself at multiple nodes of a suffix tree, a read-driven approach that relies on its multiple manifestations is expected to perform better. Based on this observation, we develop an algorithm, PLURIBUS, which reconciles corrections suggested by multiple manifestations of an error using a voting scheme. We compare the accuracy of PLURIBUS in detecting and correcting errors against existing error correction techniques using simulated sequencing data. We also assess the impact of error correction on the performance of sequence assembly. Our results show that PLURIBUS corrects errors with improved precision and enables the assembler to generate longer contigs, particularly when the genome is longer, or coverage is lower. PLURIBUS is freely available at http://compbio.case.edu/pluribus/.

In this paper, two approaches are evaluated using the Full Error Detection and Correction (FEDC) method for a pipelined structure. The approaches are referred to as Full Duplication with Comparison (FDC) and Concurrent Checking with Parity Prediction (CCPP). Aforementioned approaches are focused on the borderline cases of FEDC method which implement Error Detection Circuit (EDC) in two manners for the purpose of protection of combinational logic to address the soft errors of unspecified duration. The FDC approach implements a full duplication of the combinational circuit, as the most complex and expensive implementation of the FEDC method, and the CCPP approach implements only the parity prediction bit, being the simplest and cheapest technique, for soft error detection. Both approaches are capable of detecting soft errors in the combinational logic, with single faults being injected into the design. On the one hand, the FDC approach managed to detect and correct all injected faults while the CCPP approach could not detect multiple faults created at the output of combinational circuit. On the other hand, the FDC approach leads to higher power consumption and area increase compared to the CCPP approach.

Implementation and Analysis of Methods for Error Detection and Correction on FPGA

Space computing systems commonly use field-programmable gate arrays to provide fault tolerance by applying triple modular redundancy (TMR) to existing register-transfer-level (RTL) code. Although effective, this approach has a 3× area overhead that can be prohibitive for many designs that often allocate resources before considering effects of redundancy. Although a designer could modify existing RTL code to reduce resource usage, such a process is time consuming and error prone. Integrating redundancy into high-level synthesis is a more attractive approach that enables synthesis to rapidly explore different tradeoffs at no cost to the designer. In this paper, we introduce a scheduling and binding heuristic for high-level synthesis that explores tradeoffs between resource usage, latency, and the amount of redundancy. In many cases, an application will not require 100% error correction, which enables significant flexibility for scheduling and binding to reduce resources. Even for applications that require 100% error correction, our heuristic is able to explore solutions that sacrifice latency for reduced resources, and typically save up to 47% when relaxing the latency up to 2×. When the error constraint is reduced to 70%, our heuristic achieves typical resource savings ranging from 18% to 49% when relaxing the latency up to 2×, with a maximum of 77%. Even when comparing with optimized RTL designs, our heuristic uses up to 61% fewer resources than TMR.

Offset, gain and time mismatch errors exist in the channels of the time-interleaved analog-to-digital converter (TIADC), which severely affect the signal-to-noise and distortion ratio (SNDR), spurious-free dynamic range (SFDR) and effective number of bits (ENOB). Here, an error detection and correction method of TIADC based on genetic algorithm (GA) optimization is presented. The algorithm based on sine fitting is used for the first estimation and rough correction of the input signal, and GA is used for the second detection and fine correction of channel mismatch errors on the signal after frequency domain filtering. Experimental results show that the SNDR of the TIADC system is enhanced to 92.24 dB, the SFDR is enhanced to 102.05 dB, the ENOB is enhanced to 15.03 bits and the spectrum spurs are reduced. This method provides a new idea for error detection and correction of high-resolution TIADC systems with more than 16 bits.

Quantum error correction plays a vital role in the Quantum information process. Nowadays, the research has been increased in quantum technology and is being applied in various applications like secure communications, finance, machine learning, drug analysis and etc. But the quantum information process is difficult compared to the classical due to the challenges in quantum technology like no-cloning theorem, decoherence, and the difficulty in quantum states measurement. Thus the error rate is high and it is not possible to build a quantum computer without an error detection and correction mechanism. In this paper, we are discussing various error correction methods and proposing a novel encoding method for quantum error correction.

PurposePower consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.Design/methodology/approachIn this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.FindingsExperimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.Originality/valueThe proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

The time difference method based ultra-high-frequency (UHF) partial discharge (PD) localization has not been extensively applied in substations due to its excessive localization error. A novel and effective PD localization error correction method, consisting of two multiple radial basis function (RBF) networks, RBF t for time delay error correction and RBF p for PD position error correction, is reported in this paper as a solution. Furthermore, the RBF t , trained by time delay value measured in field experiments and RBF p , trained by the localization results corrected by RBF t , have both adopted the multiple neural networks structure which could further improve their error correction ability. The field tests proved that, the error correction networks RBF t and RBF p have strong ability to learn and simulate the error distribution. After the error correction and compensation, the PD distance localization error is reduced from 3m to 0.5m and the direction angle error is reduced from 12° to less than 5°. Universality experiments also revealed that the proposed method has a good adaptability for different time-delay algorithms and different types of PD models, which proved the robustness and effectiveness of proposed method.

The transmission of communication signals must not only ensure the speed of transmission, but also ensure the accuracy of transmission. The current research has been able to draw the advantages and disadvantages of the application of different error-correcting codes. However, it is not enough to simply compare transmission performance between different error correction code applications. Therefore, this paper uses MATLAB to simulate the transmission environment of the real channel, analyzes the reception error of short-length data through QPSK coding and IQ modulation, and analyzes the signal transmission using error correction code (Hamming code) and error detection code (even check code). The transmission performances were explored and compared, and their anti-noise interference performance was analyzed. Studies have shown that for short-length data, the error correction method using Hamming code can resist limited noise interference, but it can save bandwidth and increase the proportion of effective signal bits. In the low signal-to-noise ratio case, the method of using even-check code to detect errors has problems. Errors may be generated, and the proportion of effective signal bits is low, but the adaptability to noise is stronger than the previous method. Therefore, it is recommended to select different transmission methods for transmission environments with different signal-to-noise ratio ranges, and the combination of the two may further improve the anti-noise interference capability of signal transmission.

BackgroundInnumerable opportunities for new genomic research have been stimulated by advancement in high-throughput next-generation sequencing (NGS). However, the pitfall of NGS data abundance is the complication of distinction between true biological variants and sequence error alterations during downstream analysis. Many error correction methods have been developed to correct erroneous NGS reads before further analysis, but independent evaluation of the impact of such dataset features as read length, genome size, and coverage depth on their performance is lacking. This comparative study aims to investigate the strength and weakness as well as limitations of some newest k-spectrum-based methods and to provide recommendations for users in selecting suitable methods with respect to specific NGS datasets.MethodsSix k-spectrum-based methods, i.e., Reptile, Musket, Bless, Bloocoo, Lighter, and Trowel, were compared using six simulated sets of paired-end Illumina sequencing data. These NGS datasets varied in coverage depth (10× to 120×), read length (36 to 100 bp), and genome size (4.6 to 143 MB). Error Correction Evaluation Toolkit (ECET) was employed to derive a suite of metrics (i.e., true positives, false positive, false negative, recall, precision, gain, and F-score) for assessing the correction quality of each method.ResultsResults from computational experiments indicate that Musket had the best overall performance across the spectra of examined variants reflected in the six datasets. The lowest accuracy of Musket (F-score = 0.81) occurred to a dataset with a medium read length (56 bp), a medium coverage (50×), and a small-sized genome (5.4 MB). The other five methods underperformed (F-score < 0.80) and/or failed to process one or more datasets.ConclusionsThis study demonstrates that various factors such as coverage depth, read length, and genome size may influence performance of individual k-spectrum-based error correction methods. Thus, efforts have to be paid in choosing appropriate methods for error correction of specific NGS datasets. Based on our comparative study, we recommend Musket as the top choice because of its consistently superior performance across all six testing datasets. Further extensive studies are warranted to assess these methods using experimental datasets generated by NGS platforms (e.g., 454, SOLiD, and Ion Torrent) under more diversified parameter settings (k-mer values and edit distances) and to compare them against other non-k-spectrum-based classes of error correction methods.

This paper presents a hazard-free design methodology for the design of asynchronous sequential circuits based on a combination of synchronous and asynchronous circuit elements. Earlier approaches to essential hazard-free design of asynchronous sequential circuits are based on any one of the two design philosophies: by the addition of delay elements to the state output, or by input gate modification. The former approach makes the whole design slower. On the other hand, the latter approach is based on the assumption that the gate delays are always higher than any wire delay present in the network, but in VLSI circuits the above assumption may not be true. The design in this paper makes no assumption about the delays of the network and hence is applicable to any environment. In addition, the design in this paper uses the minimum number of self-synchronous transitions, thus making it faster than the earlier designs.