Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

This paper presents a hazard-free design methodology for the design of asynchronous sequential circuits based on a combination of synchronous and asynchronous circuit elements. Earlier approaches to essential hazard-free design of asynchronous sequential circuits are based on any one of the two design philosophies: by the addition of delay elements to the state output, or by input gate modification. The former approach makes the whole design slower. On the other hand, the latter approach is based on the assumption that the gate delays are always higher than any wire delay present in the network, but in VLSI circuits the above assumption may not be true. The design in this paper makes no assumption about the delays of the network and hence is applicable to any environment. In addition, the design in this paper uses the minimum number of self-synchronous transitions, thus making it faster than the earlier designs.

As the synchronous circuit design is facing some limits, such as the power wall and the clock skew problem, the asynchronous circuit design is approaching a revival. This paper presents a coarse-grained data-driven design flow for asynchronous circuits, which aims at both performance and design efficiency. Based on a set of data-driven components, pipelined asynchronous circuits can be efficiently constructed. We optimize the circuits by combining components to form coarse-grained pipelines. Experimental results on an asynchronous pipelined 32-bit iterative multiplier show the efficiency of our design flow.

A new asynchronous wrapper circuit is proposed based on standard cells for the realization of point to point high speed seamless data transmission. The wrapper is realized from the Signal Transition Graph (STG) by Petrify based on the fundamental GALS system structure. The asynchronous circuit includes the design of synchronous/asynchronous interface and local clock which can be suspended. The traditional EDA tools are merged together with asynchronous circuit design, and the wrapper only has standard cells but not special asynchronous logic gates. The simulation and verification were made by Modelsim and Quartus respectively, and the results have shown that the GALS system works properly and has a preferable performance.

The roadblock to wide acceptance of asynchronous methodology is poor CAD support. Current asynchronous design tools require a significant re-education of designers, and their features are far behind synchronous commercial tools. This paper considers a particular subclass of asynchronous circuits (null convention logic or NCL) and suggests a design flow that is based entirely on commercial CAD tools. This new design flow shows a significant area improvement over known flows based on NCL.

Asynchronous circuits are a promising type of digital circuit that still see moderate usage in today’s commercial products, which has often been linked to the adaptation challenges that are posed within industry, e.g. time required to develop new tools and train designers versus using existing synchronous tools to quickly meet market demands. Several formal models were introduced to aid with the design of asynchronous circuits, including Burst-Mode (BM) Specifications and Signal Transition Graphs (STGs). BM specifications resemble synchronous Finite State Machines (FSMs) allowing circuit designers to easily adapt and use them, however their circuit implementations may be limited due to declining tool support. STGs have access to well-established tools that produce optimal hazard-free circuit implementations, but they are seen as too different by the industry. In this paper, we present a new ‘co-design’ methodology that bridges the gap between BM specifications and STGs by using a formal model called Burst Automaton (BA). BA is a generic FSM-like model that acts as a framework for enabling interoperability between many different formal models, and offers several benefits that BM specifications and STGs can leverage. Our ‘co-design’ methodology is implemented in Workcraft, and is evaluated on several benchmarks showing an improved synthesis flow.

Asynchronous systems are designed without any global clock signal. Here computation is achieved by a series of events represented by signal transition edges; hence the speed of computation is determined by the signal propagation delay of the asynchronous circuit and not on the global clock. Some notable problems in synchronous circuit design due to higher performance demand are clock skew, power dissipation and worst case performance. The asynchronous circuit design which generally does not suffer from these problems, is experiencing a significant resurgence of interest and research activity. In this work, we propose analysis and design of reversible Hazard free latches for the first time in Reversible literature. Two methods are proposed for static hazard removal. Then performance parameters of these two methods are then compared. We also propose design of 4-bit up/down Asynchronous counter. All the proposed designs are functionally verified using Xilinx ISE simulator with their designs coded in the Verilog HDL.

The design of asynchronous sequential circuits is commonly related to the problem of observing some specific timing constraints to avoid unreliable behaviour. State assignment and hazard-free construction of the combinational circuits for the state transition equations are the most essential topics to investigate. They contribute significantly to the design, particularly in comparison with that of synchronously operated systems. On the other hand, the application of digital circuitry for solving control tasks implies more and more asynchronous interaction between the controller and the controlled unit, and also the use of modern, highly-integrated modules. This paper investigates the possibility of applying arbitrarily chosen, but unique, codes for state assignments, using l.s.i. memories and programmable logic arrays for implementing more complex asynchronous sequential circuits than is possible with discrete or s.s.i/m.s.i. components. A basic model is derived to describe the time properties of such matrix arrays, and design rules are established to decide easily by some simple measurements, if a given module may be used in that application. The results of a broad investigation into available memories and field-programmable logic arrays show that reliable asynchronous sequential circuits may be implemented without having hazard problems and the need for special state-assignment procedures.

In this chapter, we present applications of regions and elementary (or quasielementary) net synthesis for the design of speed independent circuits. Asynchronous circuit design is a wide and complex field that encompasses other topics than Petri nets. We refer the reader to the book [46] for a complete presentation of this field. We will limit ourselves to assessing the roles played by regions and net synthesis for solving the Complete State Coding problem (CSC). This crucial problem motivated the implementation of a net synthesis procedure in Petrify, a general design tool for asynchronous circuits presented in [46]. It must be acknowledged that different methods based on net unfoldings and SAT solvers are now preferred over net synthesis for solving the CSC problem.

The proposed CAD process simplifies the task of designing asynchronous sequential logic circuits (ASLCs). It provides a highly structured, interactive approach for modeling ASLCs and for mapping these models into architectures and gate-level circuits. This task-oriented system provides a convenient way to describe the design specification. It can also be used to facilitate the investigation of alternative ASLC architectures for purposes of optimizing a given design.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cach memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

From the Publisher: This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world’s leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

Synthesis of asynchronous circuits from signal transition graphs (STGs) involves resolution of state encoding conflicts by means of refining the STG specification. The refinement process is generally done automatically using heuristics. It often produces suboptimal solutions or sometimes fails to solve the problem. Thus manual intervention by the designer may be required. A framework is presented for an interactive refinement process aimed to help the designer. It is based on the visualisation of conflict cores, i.e. sets of transitions causing encoding conflicts, which are represented at the level of finite and complete prefixes of STG unfoldings.

Asynchronous circuit design is a beautiful application area for any formalism that can reason about parallelism By means of two small, but challenging, exercises we illustrate the similarities and differences between parallel program and asynchronous circuit design. The exercises are simple to state and have many solutions, which are sometimes surprisingly efficient. They all illustrate many aspects of asynchronous circuit design. For each exercise we present several solutions, which are analysed with respect to delay assumptions, safety, progress, and performance issues. We also mention some open problems.KeywordsPower ConsumptionCommunication BehaviorParallel CompositionArea ComplexityProgress ConditionThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Asynchronous systems are being viewed as an increasingly viable alternative to purely synchronous systems. This paper gives an overview of the current state of the art in practical asynchronous circuit and system design in four areas: controllers, datapaths, processors, and the design of asynchronous/synchronous interfaces.