Circuit Styles for Logics

From the Publisher: This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world’s leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cach memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

As demand rises for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used in the semiconductor industry, as evidenced by the International Technology Roadmap for Semiconductors' (ITRS) prediction of a likely shift from synchronous to asynchronous design styles in order to increase circuit robustness, decrease power, and alleviate many clock-related issues 1 .ITRS predicts that asynchronous circuits will account for 19% of chip area within the next 5 years, and 30% of chip area within the next 10 years 2 .To meet this growing industry need, students in Computer Engineering should be introduced to asynchronous circuit design to make them more marketable and more prepared for the challenges faced by the digital design community for years to come. DI Register DI CombinationalLogic

We have developed a method of simplifying physical design for undergraduates enrolled in analog VLSI design. The analog CMOS course is a VLSI design course with laboratory that includes design, fabrication and testing of analog CMOS circuits. A student's design begins with a simple current mirror and ends with different types of sampling circuits such as switched-capacitor and autozero circuits. The layout of thest parts is simplified by using cells similar to those used for analog stack generators. By introducing this course, more advanced digital VLSI courses can be taught at the undergraduate level, including those with larger projects.

PurposePower consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.Design/methodology/approachIn this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.FindingsExperimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.Originality/valueThe proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

The Air Force Institute of Technology, like many other schools, uses the Berkeley Tool Set for chip layout in VLSI design courses. One of the important tools of this set is the layout editor, MAGIC. Designing at the mask level is one of the important aspects of a VLSI design course, as it allows students to get a feel for what kinds of decisions and design trade-offs must be made in creating a circuit. One of the drawbacks of using a layout editor, such as MAGIC, is the amount of time it takes students to learn the interface to the tool, and the resistance to having to memorize a long list of commands or macros. To overcome this drawback, we have created a graphical user interface using Tooltool.

An attempt has been made to introduce VLSI design education into the traditional undergraduate electrical engineering curriculum at the State University of New York, New Paltz, through an innovative one-semester digital VLSI design course sequence. The emphasis in VLSI education is on full custom design, thereby exposing undergraduate students to the lower levels of design. The course is compatible with the requirements of the MOSIS silicon foundry for chip fabrication.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

This paper presents a hazard-free design methodology for the design of asynchronous sequential circuits based on a combination of synchronous and asynchronous circuit elements. Earlier approaches to essential hazard-free design of asynchronous sequential circuits are based on any one of the two design philosophies: by the addition of delay elements to the state output, or by input gate modification. The former approach makes the whole design slower. On the other hand, the latter approach is based on the assumption that the gate delays are always higher than any wire delay present in the network, but in VLSI circuits the above assumption may not be true. The design in this paper makes no assumption about the delays of the network and hence is applicable to any environment. In addition, the design in this paper uses the minimum number of self-synchronous transitions, thus making it faster than the earlier designs.

Asynchronous processors, which do not require an external clocking signal, give better performance than comparable synchronous processors in situations for which global synchronization with a high-speed clock becomes a limiting factor to system throughput. Automatic synthesis and the ability to decouple the timing considerations from the design of computational blocks make this approach particularly attractive in reducing design effort when systems become complex. A number of issues relevant to asynchronous programmable processors such as interconnection circuit specifications, circuit design, data flow control, program flow control, feedback and initialization, and I/O interface are discussed. >

This chapter discusses different VLSI design techniques highlighting coding style for synthesis. It covers important design concepts like synchronous and asynchronous circuits, clock and reset circuits, clock domain crossovers, speed matching, and so on. In addition, it deals with behavioral modelling, structural modelling, standard cell libraries, and different file formats generated during design phases with SOC design context. The reader is advised to refer VLSI logic design books (A Verilog HDL primer, J Bhaskar; VHDL primer Jayaram Bhaskar, A System Verilog primer, J Bhaskar) for fundamental understanding of VLSI design and books on hardware description languages like Verilog and VHDL for clear understanding and mastering them.

In the present scenario, designing a circuit with low power has become very important and challenging task, low power devices are the need of present electronics industries. In VLSI circuit design, power dissipation and leakage present are the critical design structures as they show anvital role in act of the battery. Power management of chip is the major challenge. Leakage power is a crucial parameter as the technology is shrinking (180 nanometer, 90 nanometer, 45 nanometer).The leakage current is increasing very fast so numerous technique has been proposed for leakage reduction in CMOS digital integrated circuit. This review paper demonstrates the various reduction showcase for CMOS integrated circuited.

Conventional active noise cancelling (ANC) headphones perform well in reducing the low-frequency noise and isolate high-frequency noise by earmuffs passively. These systems often use high-speed digital signal processors (DSPs) to cancel out the disturbing noise at such low frequencies, which result in a high-power dissipation for a commercial ANC headphone. This paper proposes a high-performance feedforward ANC architecture and implements a high-performance low power circuit design accordingly based on the filtered-x least mean square (FxLMS) adaptive algorithm. Experimental results show that the proposed high-performance circuit design can reduce disturbing noise of various frequency bands very well, and outperforms the existing works. After fabricating by using the TSMC 90nm CMOS technology, the proposed design can attenuate 15 dB for the broadband pink noise between 50–1500 Hz when operated at 10 MHz clock frequency at the costs of 84.2 k gates and power consumption of 6.42 mW only.

Synchronous very large-scale integration (VLSI) design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. Recently, there has been a resurgence of interest in asynchronous design techniques due to the significant potential benefits that the elimination of global synchronization may offer to issues such as clock distribution, power consumption, performance, and modularity. Modeling and simulation may perform a catalytic role in the quest for the realization of the potential offered by asynchronous logic. Hence, the recurrence of interest in asynchronous design has been accompanied by intense research activity aimed at developing notations and techniques appropriate for modeling and simulating asynchronous systems. Communication sequential processes and its executable counterpart, occam, are increasingly advocated as particularly suitable for this purpose. This article discusses the modeling of an asynchronous microprocessor using occam.

Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example

In any cell-based design methodology, usually, a library of cells is designed without prior knowledge of where each cell may be used. The cells from the library are placed and routed to construct the physical implementation of a circuit. The cells are designed to minimize the layout area and a little consideration is given to the location of the interface terminals. This can hinder the design of high performance circuits as the routing phase may produce interconnects with excessive signal delays. We present a new top-down design flow in which the contents of leaf cells are constructed after the cell placement has been done, with area minimization as the primary goal. Based on this placement, we design the locations of interface terminals for the leaf cells. Our proposed method optimizes leaf cell interface on the basis of cell placement and global interconnect. Our experiments show that, with this new technique, we can achieve denser and high performance layouts. Our algorithm for planning of terminal locations minimizes the number of master cells needed for multiple instances of cells, thus minimizing the cell layout effort. Our results show a reduction in total manhattan net length of 28%-75%, which implies a decrease in interconnect delays and does not cause significant increase in cell area.