Quadruple time redundancy adders [error correcting adder

Presents an enhanced concurrent error correcting arithmetic unit design methodology using alternating logic, which is motivated by the time shared triple modular redundancy (TMR) technique. With help from alternating logic, this new design approach will result in a higher reliability, i.e., 100% stuck-at faults can be detected, modest hardware delay and overhead. The basic idea is to add inverters and multiplexers in front of and behind the arithmetic unit and to let some control logic choose the path for the data. This design methodology can be applied to any system with hardware redundancy. For demonstration and comparison, 16-bit VLSI ripple carry adders are designed and verified using both the time shared TMR technique and the time shared TMR with alternating logic strategy. It is shown from the simulation results that the proposed approach has higher reliability with only a small increase in hardware delay.

Urban buildings use a large amount of electrical energy every day, especially for cooling. One common reason Fault tolerance is a critical requirement in safety-critical and high-reliability digital systems such as aerospace electronics, medical devices, industrial automation, and communication infrastructure. This project focuses on the design and development of a fault-tolerant digital system using the Triple Modular Redundancy (TMR) technique [1], [3]. In a TMR architecture, three identical modules execute the same operation in parallel, and a majority voting mechanism determines the correct output even if one module fails due to transient faults, permanent hardware failures, or radiation-induced errors [1]. The proposed system implements replication at the hardware level and incorporates a robust majority voter circuit to ensure continuous operation without performance degradation [2], [3]. The design is simulated and validated using digital design tools to analyze system behavior under fault-injection scenarios. Performance metrics such as reliability, error-masking capability, propagation delay, and resource utilization are examined to evaluate the effectiveness of the TMR approach. The results demonstrate that TMR significantly enhances system reliability and resilience by masking single-point failures, making it a practical solution for mission-critical applications where system downtime or incorrect outputs are unacceptable [1], [3]. This project provides a comprehensive understanding of fault-tolerant design strategies and highlights the trade-offs between hardware redundancy, system complexity, and operational reliability.

This study presents an improved convergent distributed arithmetic (DA)‐based low complexity pipelined least‐mean‐square filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step‐sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA‐based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bit‐level coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low‐cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time‐window corresponding to the maximum correlation of delayed error signals with a pre‐defined window with n being time instant and . Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th‐order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip‐area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area‐delay‐product and 4.76% less energy‐per‐sample for 64th order with the fourth‐order base unit over the best existing scheme.

Advances in nanoelectronic fabrication have enabled integrated circuits to operate at a high frequency. The finite impulse response (FIR) filter needs only to meet real-time demand. Accordingly, increasing the FIR architecture's folding number can compensate the high-frequency operation and reduce the hardware complexity, while continuing to allow applications to operate in real time. In this work, the folding scheme with integrating input-data and tap folding is proposed to develop a hardware-efficient programmable FIR architecture. With the use of the radix-4 Booth algorithm, the 2-bit input subdata approach replaces the conventional 3-bit input subdata approach to reduce the number of latches required to store input subdata in the proposed FIR architecture. Additionally, the tree accumulation approach with simplified carry-in bit processing is developed to minimize the hardware complexity of the accumulation path. With folding in input data and taps, and reduction in hardware complexity of the input subdata latches and accumulation path, the proposed FIR architecture is demonstrated to have a low hardware complexity. By using the TSMC 0.18 µm CMOS technology, the proposed FIR processor with 10-bit input data and filter coefficient enables a 128-tap FIR filter to be performed, which takes an area of 0.45mm2, and yields a throughput rate of 20M samples per second at 200 MHz. As compared to the conventional FIR processors, the proposed programmable FIR processor not only meets the throughput-rate demand but also has the lowest area occupied per tap.

The authors present a reformulation based architecture for threshold selection in adaptive foward error correction (FEC) decoding in wireless applications. The reformulation technique results in an efficient VLSI architecture with a significant reduction in hardware complexity. The paper describes the reformulation technique, its applications on the architecture for adaptive forward error correction (FEC) decoding algorithm and its implementations. We demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric unit (PMU).

A novel design and implementation technique for low complexity variable digital filters using multi-objective artificial bee colony optimization and a minimal spanning tree approach

A vehicle accident report system was designed to detect accidents accurately and send message to related person. However, after accident, some components or modules can be damaged and it may cause failure of accident detection. Therefore, Triple Modular Redundancy (TMR) method was implemented in the system to mask faults within the modules and ensure the system to continue working. TMR is one of passive hardware redundancy methods. The system includes three MPU-6050 sensors functioning as vehicle tilt sensors to provide hardware redundancy, a TC9548A module serving as an I2C multiplexer, an Arduino Nano acting as a microcontroller and voter, and a NodeMCU ESP8266 responsible for transmitting message. Based on experiment results, the TMR system has a reliability value of 0.9928, a failure rate value of 0.0004/cycle, and accuracy of 3 sensor value of 85%. While, the non-redundancy system has a reliability value of 0.9286, a failure rate value of 0.0053/cycle, and accuracy of single sensor value of 57%. The results of the system process were sent to and displayed via an e-mail. It can be concluded that the TMR system has better performance than the non-redundancy one.

In the past, hardware realization of digital signal processing elements have been based upon binary arithmetic concepts. Because of the dependence between digits in binary arithmetic operations, the hardware required to construct arithmetic elements is cumbersome. In the residue number system, arithmetic operations can be performed with complete independence between digits and a corresponding reduction in hardware complexity. In fact, using current technology, arithmetic operations can be carried out using arrays of look-up tables placed in high density ROMs. This paper discusses the application of the residue number system to realizing digital signal processing elements using such arrays and advantages and disadvantages over conventional realizations are discussed. Examples are given of recursive filter and FFT butterfly element realization.

We present a novel and efficient approach to true-time-delay (TTD) beamforming for large adaptive phased arrays with N elements, for application in radar, sonar, and communication. This broadband and efficient adaptive method for time-delay array processing algorithm decreases the number of tapped delay lines required for N-element arrays form N to only 2, producing an enormous savings in optical hardware, especially for large arrays. This new adaptive system provides the full NM degrees of freedom of a conventional N element time delay beamformer with M taps, each, enabling it to fully and optimally adapt to an arbitrary complex spatio-temporal signal environment that can contain broadband signals, noise, and narrowband and broadband jammers, all of which can arrive from arbitrary angles onto an arbitrarily shaped array. The photonic implementation of this algorithm uses index gratings produce in the volume of photorefractive crystals as the adaptive weights in a TTD beamforming network, 1 or 2 acousto-optic devices for signal injection, and 1 or 2 time-delay-and- integrate detectors for signal extraction. This approach achieves significant reduction in hardware complexity when compared to systems employing discrete RF hardware for the weights or when compared to alternative optical systems that typically use N channel acousto-optic deflectors.

In this paper, we propose an efficient controller design of barrel shifter for reconfigurable low-density parity-check (LDPC) decoders, which leads to significant reduction in hardware complexity. Since the structured LDPC codes for the most modern wireless communication systems include multiple code rates, various block lengths, and different sizes of submatrices, a reconfigurable LDPC decoder is desirable and the barrel shifter needs to be programmable. Even though the Benes network can be optimized for the barrel shifting networks of reconfigurable LDPC decoder, it is not trivial to generate all the control signals for numerous 2times2 switches on-the-fly. A novel simplified algorithm capable of generating all the control signals is proposed using the properties that both the full-size Benes network can be broken into two half-size Benes networks and the barrel shifters needed in the structured LDPC decoders require only cyclic shifts. The proposed algorithm can be easily implemented with a small numbers of gates. Compared with the direct implementation using a dedicated look-up table, the proposed algorithm achieves a significant hardware reduction in implementing a reconfigurable LDPC decoder.

The architectural design of the proposed IF digital frequency down converter (DFDC) is the combination of 4-IF oversampling and multistage interpolated finite impulse response filter design techniques based on a multirate algorithm. It can have very low-power dissipation owing to the reduction in hardware complexity and operational frequency. Design application for an IS-95 CDMA with IF frequency at 4.9152 MHz shows that the DFDC only consumes 0.6 mW when operated at 2 V.

The authors discuss the implementation of a computationally efficient two stage echo cancellation system for high speed data transmission. In addition to a substantial reduction in hardware complexity, the two stage echo canceller offers the advantage of a speedier convergence compared to the conventional FIR filter.

Stochastic computing allows a drastic reduction in hardware complexity using serial processing of bit streams. While the induced high computing latency can be overcome using integrated optics technology, the design of realistic optical stochastic computing architectures calls for energy efficient switching devices. Photonics Crystal (PhC) nanocavities are μm 2 scale devices offering 100fJ switching operation under picoseconds-scale switching speed. Fabrication process allows controlling the Quality factor of each nanocavity resonance, leading to opportunities to implement architectures involving cascaded gates and multi-wavelength signaling. In this paper, we investigate the design of cascaded gates architecture using nanocavities in the context of stochastic computing. We propose a transmission model considering key nanocavity device parameters, such as Quality factors, resonance wavelength, and switching efficiency. The model is calibrated with experimental measurements. We propose the design of XOR gate and multiplexer. We illustrate the use of the gates to design an edge detection filter. System-level exploration of laser power, bit-stream length and bit-error rate is carried out for the processing of gray-scale images. The results show that the proposed architecture leads to 8.5nJ/pixel energy consumption and 512ns/pixel processing time.

Nonbinary low-density parity-check (NB-LDPC) codes offer a superior error correction capability compared to the existing binary counterparts. However, there exist two major disadvantages in NB-LDPC decoders that they require substantial hardware resources, particularly at the check node unit (CNU), and high latency in the decoding process. In this brief, a novel minimal-set trellis min-max (MS-TMM) algorithm for NB-LDPC decoders is proposed to reduce the complexity of the CNU and enhance the decoding throughput. The decoder architecture based on the proposed MS-TMM algorithm is implemented for the (837, 726) NB-LDPC code over Galois field GF(32) using 90-nm CMOS technology. The implementation results show that the proposed architecture offers a great reduction in hardware complexity and highest efficiency compared to the state-of-the-art works. Additionally, the proposed decoder architecture is able to achieve a throughput of 1.704 Gbps and 2.254 Gbps at eight and six iterations respectively, which is a considerable improvement compared to the previous works.

A novel design is presented about ROM-less direct digital frequency synthesizer (DDFS) using phase to sinusoid amplitude conversion blocks based on the two segment fourth-order parabolic approximation. The mathematical maximum error analysis shows that the resolution is up to 14 bits. In order to reduce the hardware complexity without sacrificing speed, the squarer and constant multipliers have been decomposed and optimized. The whole architecture has been split into twenty pipelining stages with a 200 MHz clock rate and a single phase output up to 50 MHz. Meanwhile, because the sine and cosine phase to amplitude modules share the same hardware, reduction of hardware complexity and power consumption can be achieved. Spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is about -90 dBc. The implementation demonstrates that the proposed DDFS architecture can be realized with a smaller hardware scale and lower power consumption than many other existing approaches.