Low-power multirate IF digital frequency down converter

Advances in nanoelectronic fabrication have enabled integrated circuits to operate at a high frequency. The finite impulse response (FIR) filter needs only to meet real-time demand. Accordingly, increasing the FIR architecture's folding number can compensate the high-frequency operation and reduce the hardware complexity, while continuing to allow applications to operate in real time. In this work, the folding scheme with integrating input-data and tap folding is proposed to develop a hardware-efficient programmable FIR architecture. With the use of the radix-4 Booth algorithm, the 2-bit input subdata approach replaces the conventional 3-bit input subdata approach to reduce the number of latches required to store input subdata in the proposed FIR architecture. Additionally, the tree accumulation approach with simplified carry-in bit processing is developed to minimize the hardware complexity of the accumulation path. With folding in input data and taps, and reduction in hardware complexity of the input subdata latches and accumulation path, the proposed FIR architecture is demonstrated to have a low hardware complexity. By using the TSMC 0.18 µm CMOS technology, the proposed FIR processor with 10-bit input data and filter coefficient enables a 128-tap FIR filter to be performed, which takes an area of 0.45mm2, and yields a throughput rate of 20M samples per second at 200 MHz. As compared to the conventional FIR processors, the proposed programmable FIR processor not only meets the throughput-rate demand but also has the lowest area occupied per tap.

It has been shown by some researchers that in a problem of weighted least-square (WLS) design of finite-impulse response (FIR) filters, bulk of the design computation is concerned with the evaluation of the inverse of a matrix in order to solve a system of equations. In this paper, a new algorithm for the WLS design of FIR filters is presented, in which an iterative procedure is developed for the inversion of the matrix involved in the design. By imposing a mild constraint on the updation factor of the weighting function, the inverse of a matrix is expanded as a convergent power series. By investigating the properties of some of the matrices from the design formulation, a modified version of the series that converges rapidly is then proposed to evaluate the inverse in each iteration. It is shown that due to the fast convergence of the power series, one needs to evaluate only the first two or three terms of the series except during the initial stages of the iterations, implying that the conventional operation for matrix inversion is simplified significantly.

Digital filters play a central role in modern Digital Signal Processing (DSP) systems. Finite Impulse Response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

Digital filters play a central role in modern digital signal processing (DSP) systems. Finite impulse response (FIR) filters can provide solutions with guaranteed stability and linear phase. However, the main disadvantage of conventional FIR filter designs is that they become computationally complex, especially in applications demanding narrow transition bandwidths. Therefore, designing FIR filters with very stringent specifications and a low complexity is currently an important challenge. In this chapter, a review of the recent methods to efficiently design low-complexity linear-phase FIR filters is presented. The chapter starts with an introduction to linear-phase FIR digital filters. Then, an overview of the design methods that have been developed in literature to design low-complexity FIR filters is presented. Finally, the most common and recent of these methods along with their corresponding special structures are explained.

A novel design and implementation technique for low complexity variable digital filters using multi-objective artificial bee colony optimization and a minimal spanning tree approach

Chapter 2 - Design and Implementation of Digital FIR Filters

A novel design is presented about ROM-less direct digital frequency synthesizer (DDFS) using phase to sinusoid amplitude conversion blocks based on the two segment fourth-order parabolic approximation. The mathematical maximum error analysis shows that the resolution is up to 14 bits. In order to reduce the hardware complexity without sacrificing speed, the squarer and constant multipliers have been decomposed and optimized. The whole architecture has been split into twenty pipelining stages with a 200 MHz clock rate and a single phase output up to 50 MHz. Meanwhile, because the sine and cosine phase to amplitude modules share the same hardware, reduction of hardware complexity and power consumption can be achieved. Spectral purity analysis shows that the worst case spurious free dynamic range (SFDR) is about -90 dBc. The implementation demonstrates that the proposed DDFS architecture can be realized with a smaller hardware scale and lower power consumption than many other existing approaches.

An Finite Impulse Response (FIR) filter is a widely used digital filter technology whose impulse response has a finite duration. An FIR filter is usually favored for many reasons such as easy to design, easy to implement on a variety of system architectures. An FIR filter can be easily designed with a linear phase response and its output is more predictable since it doesn't have feedback components. There are both engineer and mathematical methods for designing an FIR filter so that machine learning doesn't play an important role in the FIR filter design. In this paper, we present an alternative to traditional filter design methods to direct learn the FIR filter coefficients from input data with machine learning algorithm. With the proposed algorithm, we can easily design an FIR filter from the input data mixed with designed all spectrum noise signal. To show the capability of this algorithm, an example application of suppressing background music from speech or vice versa is demonstrated in this paper. Despite that the music and speech have a lot of overlap in their spectrum, the filter designed by our algorithm can successfully suppress music or speech in a mixture of music and speech signals.

This study presents an improved convergent distributed arithmetic (DA)‐based low complexity pipelined least‐mean‐square filter. The concept is based on a convex combination of two adaptive filters (ADFs) where the convergence performance of the combined filter is adjusted by the step‐sizes of ADFs. The proposed technique replaced two ADF units by a single unit of the DA‐based ADF. Further reduction in hardware complexity is achieved by sharing the filter partial products. Moreover, a bit‐level coefficient update unit is employed to minimise its hardware complexity. In addition, a novel low‐cost strategy is presented to improve the convergence performance of the proposed filter by comparing the time‐window corresponding to the maximum correlation of delayed error signals with a pre‐defined window with n being time instant and . Compared with the best existing scheme, the proposed design offers 46.42% fewer adders, 36.69% fewer registers and 18.75% fewer multiplexers for a 64th‐order filter. Application specific integrated circuit synthesis results show that the proposed design occupies 37.10% less chip‐area and consumes 24.79% less power. In addition, the proposed design provides 20.35% less area‐delay‐product and 4.76% less energy‐per‐sample for 64th order with the fourth‐order base unit over the best existing scheme.

SummaryThis work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high‐performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high‐capacity hybrid (HC‐hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC‐180 nm and UMC‐65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns.

The authors present a reformulation based architecture for threshold selection in adaptive foward error correction (FEC) decoding in wireless applications. The reformulation technique results in an efficient VLSI architecture with a significant reduction in hardware complexity. The paper describes the reformulation technique, its applications on the architecture for adaptive forward error correction (FEC) decoding algorithm and its implementations. We demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric unit (PMU).

In this communication, one novel attempt has been made towards the design of minimum-phase finite impulse response (FIR) filter using one evolutionary computation technique, named differential evolution (DE) algorithm. Mean square error (MSE) between the frequency samples of the ideal filter and the designed filter in the pass-band and stop-band region and the minimum average error (MAE) between the frequency samples in the transition-band region had been considered for the formulation of the objective function in the optimization process. Performance of the optimization technique has been monitored in terms of convergence characteristics for four different orders of FIR filter under consideration. Robustness of our proposition has been firmly established in the sense that the proposed algorithm can be suitably tuned for the design of low-pass, high-pass or band-pass FIR filter of different specifications. Supremacy of the proposed algorithm over other existing techniques for the design of minimum-phase FIR filter has been substantiated by means of frequency response and pole-zero diagrams.

This paper presents a novel approach for the design of two-dimensional (2D) Finite Impulse Response (FIR) filters. The design of FIR filters is generally non-differentiable, multimodal and higher dimensional; especially for 2D filters. A large number of filter coefficients are optimized either using constrained or unconstrained optimization approach. Due to the large number of constraints, traditional design methods cannot produce optimal filters required for some crucial applications. This makes meta-heuristic algorithms as good alternatives for addressing such constraints more efficiently. In order to improve the performance of 2D filters, we propose an Accelerated Artificial Bee Colony algorithm, termed as AABC algorithm. The earlier reported ABC based methods perform the modification of a single parameter of the solution in each cycle. But in this proposed AABC algorithm, we have adopted multiple parameters change of search equation at each step. This in turn improves the convergence speed of the algorithm by three times than the classical ABC algorithm and two times with respect to recently developed CABC method. In order to achieve better exploration behaviour of abandoned bees, we have also introduced a change during the initialization strategy of scout bees in the proposed AABC algorithm. The efficiency and robustness of the proposed algorithm are demonstrated by comparing its performance with classical Genetic Algorithm (GA), Particle Swarm Optimization , ABC and CABC methods.

Nowadays, the amount of small devices performing any kind of Digital Signal Processing (DSP) has increased drastically. On the other hand, the limited energy available to such battery-powered devices is a real problem. In DSP applications, one of the most important operations is the Finite Impulse Response (FIR) filter computation. The main FIR filter characteristics are the linear phase and feed forward implementation, which make it very useful for building high stable performance filters. However, the minimal designed coefficients bit-width, in integer representation, varies for each design. The main goal of this paper is to present a power-predictive environment for fast and power-aware FIR filter design. The proposed approach searches a set of power-efficient FIR Filter during the mathematical design based on a proposed power-predictive function which is performed using both the number of taps and the bit-width of the filter. Synthesis results was performed using Cadence RTL Compiler synthesis tool for all the range of filter specifications to validate the proposed power-predictive function and the filter methodology. The main results show that the proposed power-predictive environment enables a fast and power-aware decision even in mathematical design level enabling saves in power dissipation with better filter quality, and also enabling a reduction in the time-to-market, which nowadays is a very important requirement.

Optimisation based design of finite impulse response (FIR) filters has been an active area of research for quite some time. The various algorithms proposed for FIR filter design aim at meeting a set of desired specifications in the frequency domain. Evolutionary algorithms have been found to be very effective for FIR filter design because of the non-linear, non-differentiable and non-convex nature of the associated optimisation problem. The present work proposes two modified versions of a recently developed evolutionary technique i.e. artificial bee colony (ABC) algorithm for design of FIR filters. The applicability of the proposed approach has been evaluated by comparing its response with conventional reported filter design techniques. The proposed variants of ABC are found to outperform other non-convex algorithms in achieving the desired specifications. In addition to the simulation results, the designed filters have been implemented in hardware using Xilinx-xc7vx330t-3ffg1157 (Virtex-7) field programmable gate array. The hardware implementation allows validation of the proposed techniques for practical filtering applications by considering real time operation parameters.