Performance Evaluation of Tilt-based Vehicle Accident Report System Using Triple Modular Redundancy

Using Bayesian networks in reliability evaluation for subsea blowout preventer control system

Nanoscale field-programmable gate array (FPGA) circuits are more prone to radiation-induced effects in harsh environments because of their memory-based reconfigurable logic fabric. Consequently, for mission- or safety-critical applications, appropriate fault-tolerance techniques are widely employed. The most commonly applied technique for hardening FPGAs against radiation-induced upsets is triple modular redundancy (TMR). Voting circuits used in TMR implementations are decentralized and consensus is calculated from the redundant outputs off-chip. However, if there are an insufficient number of pins available on the chip carrier, the TMR system must be reduced to an on-chip unprotected simplex system, meaning voters used at those locations become single point of failure. In this paper, we propose a self-checking voting circuit for increased reliability consensus voting on FPGAs. Through fault injection and reliability analyses, we demonstrate that the proposed voter, which utilizes redundant voting copies, is approximately 26% more reliable than an unprotected simplex voter when reliability values of voters over normalized time are averaged.

A Triple Modular Redundant (TMR) system achieves high reliability by replicating data and all processing at three independent nodes. When TMR is used for database processing all nonfaulty computers must execute the same sequence of transactions, and this is ensured by a collection of processes known as schedulers . In this paper we study the implementation of efficient schedulers through analysis of various enhancements such as null transactions and message batching. The schedulers have been implemented in an experimental TMR system and the evaluation results are presented here.

Voting Logic (VL) is an important component of Triple Modular Redundant (TMR) and N-Modular Redundant (NMR) systems. A number of voting logic designs are presented in this paper. The Design Profile, Diagnosability and Reliability calculation of a word voter for TMR system is presented.

The fault‐tolerant technique has been frequently employed to realize a highly reliable computer system. This paper considers the Triple‐Modular Redundancy (TMR) system, which is one of the fault‐tolerant systems whereby the system is partitioned into several blocks and the majority decision is made in each block. The reliability of such a system is evaluated. Based on the relation between the number of partitions and the failure rate of such a system, the following two types of models are assumed:(1) TMR network model, where the failure rate of the whole system increases with the number of partitions, when the failure rate of the block is kept constant.(2) LSI model, where the block failure rate decreases with the number of partitions, when the failure rate of the whole system is kept constant. Especially, in the model (2), the pin‐gate ratio of LSI is taken into consideration. For these models, the expression for the Mean‐Time‐To‐Failure (MTTF), which is the mean operation time until a system failure occurs, is derived. The general tendency of MTTF is analyzed. By numerical examples, the improvement of MTTF by partitioning is demonstrated. The improvement of the TMR system by partitioning is demonstrated quantitatively.

Triple modular redundancy (TMR) is one of the most common techniques in fault-tolerant systems, in which the output is determined by a majority voter. However, the design diversity of replicated modules and/or soft errors that are more likely to happen in the nanoscale era may affect the majority voting scheme. Besides, the significant overheads of the TMR scheme may limit its usage in energy consumption and area-constrained critical systems. However, for most inherently error-resilient applications such as image processing and vision deployed in critical systems (such as autonomous vehicles and robotics), achieving a given level of reliability has more priority than precise results. Therefore, these applications can benefit from the approximate computing paradigm to achieve higher energy efficiency and a lower area. This article proposes an energy-efficient approximate reliability (X-Rel) framework to overcome the aforementioned challenges of the TMR systems and get the full potential of approximate computing without sacrificing the desired reliability constraint and output quality. The X-Rel framework relies on relaxing the precision of the voter based on a systematical error bounding method that leverages user-defined quality and reliability constraints. Afterward, the size of the achieved voter is used to approximate the TMR modules such that the overall area and energy consumption are minimized. The effectiveness of employing the proposed X-Rel technique in a TMR structure, for different quality constraints as well as with various reliability bounds, is evaluated in a 15-nm FinFET technology. The results of the X-Rel voter show delay, area, and energy consumption reductions of up to 86%, 87%, and 98%, respectively, when compared to those of the state-of-the-art approximate TMR voters. Also, the effectiveness of the proposed X-Rel-based TMR structure is assessed in four benchmark applications from different domains. For these benchmarks, the results show <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.59\times $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.35\times $ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.39\times $ </tex-math></inline-formula> energy-delay-area-product (EDAP) reduction for less than 1%, 5%, and 10% output quality degradations, respectively. Finally, an image processing application is benchmarked to evaluate the X-Rel framework efficacy in the presence of errors, where the results show up to a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.78\times $ </tex-math></inline-formula> higher output image quality in comparison with the typical TMR voters.

Increasing market pressure for industrial turbine controls that reduce cost of installation, increase availability, and reduce overall installation and commissioning time have driven systems in a new direction. This direction is away from complex and expensive triplex or TMR (Triple Modular Redundant) systems and towards dual redundant and networked control systems. Woodward’s core fuel and combustion control is currently being used in a networked system for GE’s LM2500 aeroderivative gas turbine packages. This networked control system utilizes redundant high-speed communications from the sequencer to fuel control. Packaging I/O is also distributed over redundant communications to localize wiring. The fuel control communicates to the gas metering valves and gas turbine variable geometry servo-valves to reduce wiring and installation time. This control system utilizes simplex CPU’s to save cost and duplex hardware and communications for availability. Expansion of this to full redundant CPU processing capabilities can also be achieved to add availability with some cost tradeoff. Woodward has also applied this full redundancy concept in the commercial marine GE LM2500 package applications. In addition to using network communications the core fuel control system is in itself networked, being “package” mounted. Mounting the fuel control on the package reduces the number of field installation wire terminations and the total length of wire used between the gas turbine and the fuel control. Having the main fuel control system mounted on the package allows the control to be wired and tested at the factory rather than at site. The use of network communications in gas turbine control applications has many advantages. Reduction in overall system cost, installation and commissioning time are the main advantages to using networked controls for gas turbines. System expandability and distributed processing are other advantages. Expanding this with hardware redundancy improves availability.

Urban buildings use a large amount of electrical energy every day, especially for cooling. One common reason Fault tolerance is a critical requirement in safety-critical and high-reliability digital systems such as aerospace electronics, medical devices, industrial automation, and communication infrastructure. This project focuses on the design and development of a fault-tolerant digital system using the Triple Modular Redundancy (TMR) technique [1], [3]. In a TMR architecture, three identical modules execute the same operation in parallel, and a majority voting mechanism determines the correct output even if one module fails due to transient faults, permanent hardware failures, or radiation-induced errors [1]. The proposed system implements replication at the hardware level and incorporates a robust majority voter circuit to ensure continuous operation without performance degradation [2], [3]. The design is simulated and validated using digital design tools to analyze system behavior under fault-injection scenarios. Performance metrics such as reliability, error-masking capability, propagation delay, and resource utilization are examined to evaluate the effectiveness of the TMR approach. The results demonstrate that TMR significantly enhances system reliability and resilience by masking single-point failures, making it a practical solution for mission-critical applications where system downtime or incorrect outputs are unacceptable [1], [3]. This project provides a comprehensive understanding of fault-tolerant design strategies and highlights the trade-offs between hardware redundancy, system complexity, and operational reliability.

Presents an enhanced concurrent error correcting arithmetic unit design methodology using alternating logic, which is motivated by the time shared triple modular redundancy (TMR) technique. With help from alternating logic, this new design approach will result in a higher reliability, i.e., 100% stuck-at faults can be detected, modest hardware delay and overhead. The basic idea is to add inverters and multiplexers in front of and behind the arithmetic unit and to let some control logic choose the path for the data. This design methodology can be applied to any system with hardware redundancy. For demonstration and comparison, 16-bit VLSI ripple carry adders are designed and verified using both the time shared TMR technique and the time shared TMR with alternating logic strategy. It is shown from the simulation results that the proposed approach has higher reliability with only a small increase in hardware delay.

Reliability is one of the most critical factors that is to be considered during the designing phase of any product. There are many factors that contribute to make a system more reliable in terms of area, power, operating frequency and accuracy. This paper proposes the design of a 4bit fault tolerant ALU system using backend designing. Parallel processing along with triple modular redundancy (TMR) has been used to increase the operating speed of the system and also to make the system fault tolerant and accurate. The backend designing has been done using Micro-wind 3.1.7

This research introduces a novel hybrid model for the step-stress accelerated life test in which the stress transitions from a low level to a high level following a certain number of failures or a pre-determined time, whichever comes first. The stress is applied to the triple modular redundancy system, in which each device has a lifetime subjecting to the exponential distribution. This hybrid model significantly reduces testing time under a designated stress level. The test study also examines a simple step-stress testing scenario, concluding based on the type-II censoring scheme. Stress elevation follows the tampered hazard rate model. To estimate the reliability of the triple modular redundancy system and its mean time to failure, point and interval estimates for relevant parameters are determined using maximum likelihood and maximum product of spacings methods. Additionally, optimal timing for raising applied stress is explored, through two different approaches. The effectiveness of estimation methods is examined through the analysis of real-world data and Monte Carlo simulations. While both estimation methods yield convergent results, the maximum likelihood method proves to be more accurate, especially in the case of small sample sizes.

Reliability evaluation of a TMR computer system with multivariate exponential failures and a general repair

Design diversity has long been used to protect redundant systems against common-mode failures. The conventional notion of diversity relies on generation of implementations. This concept is qualitative and does not provide a basis to compare the reliabilities of two diverse systems. In this paper, for the first time, we present a metric to quantify diversity among several designs. Based on this metric, we derive analytical reliability models that show a simple relationship between design diversity, system failure rate, and mission time. In addition, we present simulation results to demonstrate the effectiveness of design diversity in Duplex and Triple Modular Redundant (TMR) systems. For independent multiple-module failures, we show that, mere use of different implementations does not always guarantee higher reliability compared to redundant systems with identical implementations-it is important to analyze the reliability of redundant systems using our metric. For common-mode failures and design faults, there is a significant gain in using different implementations-however, as our analysis shows, the gain diminishes as the mission time increases. Our simulation results also demonstrate the usefulness of diversity for enhancing the self-testing properties of redundant systems.

We investigate the implementation of triple modular redundancy (TMR) with different number of voters in a softcore RISC-V microprocessor to mitigate radiation-induced faults in the configuration memory (CRAM) of SRAM-based FPGA. The case-study microprocessor is the Steel Core implemented in AMD Xilinx 7-Series/Zynq-7000 device, executing benchmark software on the FreeRTOS operating system. We implemented coarse-grained TMR (CGTMR) and fine-grained distributed TMR (FGDTMR) using an automated redundancy and voter insertion tool. TMR is used in combination with memory scrubber featured by the FPGA hardware, which uses error correction codes (ECC) to revert radiation-induced faults in CRAM. Fault injection in CRAM emulating radiation-induced faults is used to evaluate the benefits of both TMR and ECC. Under fault injection, combining the fault masking capability of TMR with the self-healing by ECC, improved mean time between failures (MTBF) up to 5×. ECC alone did not improve significantly the fault tolerance. Without ECC, FGDTMR improves MTBF in 2×, but at a higher cost in circuit area and resources usage. When combined with ECC, the CGTMR provides fault tolerance comparable to FGDTMR but with 30% less resources usage.

Soft errors in scientific computing applications are becoming inevitable with the ever-increasing system scale and execution time, and new technologies that feature increased transistor density and lower voltage. Soft errors can be mainly classified into two categories: bit-flipping error (e.g. 1 becomes −1) in random access memory; and computation error (e.g. 1+1 = 3) in floating point units. Traditionally, bit-flipping error is handled by the Error Correcting Code (ECC) technique, and computation error is dealt with the Triple Modular Redundancy (TMR) method. Note that, ECC cannot handle computation error, while TMR cannot deal with bit-flipping error and is not efficient on handling computation error. To uniformly and efficiently handle both computation and bit-flipping errors in matrix operations, the Algorithm-Based Fault Tolerance (ABFT) method is developed. This paper focuses on the detection of soft errors in the LU Decomposition with Partial Pivoting (LUPP) algorithm, which is widely used in scientific computing applications. First, this paper notes that existing ABFT methods are not adequate to detect soft errors in LUPP in terms of time or space. Then we propose a new ABFT algorithm which can detect soft errors in LUPP both flexible in time and comprehensive in space. Flexible in time means that soft errors can be detected flexibly during the execution instead of only at the end of LUPP, while comprehensive in space indicates that all of the elements in data matrices ( L and U) will be covered for detecting soft errors. To show the feasibility and efficiency of the proposed algorithm, this paper has incorporated it into the implementation of LUPP in the widely used benchmark High Performance Linpack (HPL). Experiment results verify the feasibility of this algorithm: for soft errors injected at various timings and to different elements in LUPP, this algorithm has detected most of the injected errors, which have covered all of the errors that cannot pass the residual check of HPL. Both theoretical overhead analysis and experiments demonstrate that this ABFT algorithm is also very efficient at detecting soft errors in LUPP.