X-Rel: Energy-Efficient and Low-Overhead Approximate Reliability Framework for Error-Tolerant Applications Deployed in Critical Systems

Faults caused by ionising radiation have become a significant reliability issue in modern ICs. However, the Radiation Hardening (RADHARD) design flow differs from the standard design flow. Thus, there is not sufficient support from industrial EDA tools. In this work, we present a Triple Modular Redundancy (TMR) Radiation Hardening (RADHARD) methodology, based on the replacement of Flip-Flops (FFs) to a TMR structure, consisting of a FF triplet and a majority voter, as well as a custom, Displacement-driven legalisation algorithm, called R-Abax, able to satisfy user-specified, minimum distances between the FFs of each triplet. Our RADHARD legalisation algorithm is fully compatible with existing EDA tools. By ensuring a minimum spacing between triplet FFs of each TMR structure, we reduce the probability of a particle strike affecting more than one triplet instances. We present the impact of our RADHARD flow, for a set of spacing constraints, to Power, Performance and Area (PPA) on a set of 11 OpenCores benchmarks. On average, a larger spacing between FF triplets worsens a design's Quality-of-Results (QoR), but not significantly, making our RADHARD flow attractive for reducing radiation faults.

Soft errors in scientific computing applications are becoming inevitable with the ever-increasing system scale and execution time, and new technologies that feature increased transistor density and lower voltage. Soft errors can be mainly classified into two categories: bit-flipping error (e.g. 1 becomes −1) in random access memory; and computation error (e.g. 1+1 = 3) in floating point units. Traditionally, bit-flipping error is handled by the Error Correcting Code (ECC) technique, and computation error is dealt with the Triple Modular Redundancy (TMR) method. Note that, ECC cannot handle computation error, while TMR cannot deal with bit-flipping error and is not efficient on handling computation error. To uniformly and efficiently handle both computation and bit-flipping errors in matrix operations, the Algorithm-Based Fault Tolerance (ABFT) method is developed. This paper focuses on the detection of soft errors in the LU Decomposition with Partial Pivoting (LUPP) algorithm, which is widely used in scientific computing applications. First, this paper notes that existing ABFT methods are not adequate to detect soft errors in LUPP in terms of time or space. Then we propose a new ABFT algorithm which can detect soft errors in LUPP both flexible in time and comprehensive in space. Flexible in time means that soft errors can be detected flexibly during the execution instead of only at the end of LUPP, while comprehensive in space indicates that all of the elements in data matrices ( L and U) will be covered for detecting soft errors. To show the feasibility and efficiency of the proposed algorithm, this paper has incorporated it into the implementation of LUPP in the widely used benchmark High Performance Linpack (HPL). Experiment results verify the feasibility of this algorithm: for soft errors injected at various timings and to different elements in LUPP, this algorithm has detected most of the injected errors, which have covered all of the errors that cannot pass the residual check of HPL. Both theoretical overhead analysis and experiments demonstrate that this ABFT algorithm is also very efficient at detecting soft errors in LUPP.

Nowadays, FPGAs are used in many safety-critical applications. They are mainly subjected to Single Event Upsets (SEUs) that can flip the state of a memory cell, thereby forcing the circuit to produce an erroneous output. Fault-tolerant techniques are used to mitigate these errors. Triple Modular Redundancy (TMR) is one of the most commonly used fault-tolerant techniques in FPGAs. However, the voter is a single point of failure. This paper proposes a fault secure TMR voter design. This voter is analyzed according to its FPGA implementation. SEUs, Single Event Transients (SETs) as well as single stuck-at-0(1) faults are considered. In the presence of these faults, this voter will always produce the correct output or will give an indication of the presence of an error. Alternating Logic is utilized in the design to help with error detection while Dynamic Partial Reconfiguration (DPR) is used for error recovery.

Nanoscale field-programmable gate array (FPGA) circuits are more prone to radiation-induced effects in harsh environments because of their memory-based reconfigurable logic fabric. Consequently, for mission- or safety-critical applications, appropriate fault-tolerance techniques are widely employed. The most commonly applied technique for hardening FPGAs against radiation-induced upsets is triple modular redundancy (TMR). Voting circuits used in TMR implementations are decentralized and consensus is calculated from the redundant outputs off-chip. However, if there are an insufficient number of pins available on the chip carrier, the TMR system must be reduced to an on-chip unprotected simplex system, meaning voters used at those locations become single point of failure. In this paper, we propose a self-checking voting circuit for increased reliability consensus voting on FPGAs. Through fault injection and reliability analyses, we demonstrate that the proposed voter, which utilizes redundant voting copies, is approximately 26% more reliable than an unprotected simplex voter when reliability values of voters over normalized time are averaged.

Energy-efficient triple modular redundancy scheduling on heterogeneous multi-core real-time systems

Urban buildings use a large amount of electrical energy every day, especially for cooling. One common reason Fault tolerance is a critical requirement in safety-critical and high-reliability digital systems such as aerospace electronics, medical devices, industrial automation, and communication infrastructure. This project focuses on the design and development of a fault-tolerant digital system using the Triple Modular Redundancy (TMR) technique [1], [3]. In a TMR architecture, three identical modules execute the same operation in parallel, and a majority voting mechanism determines the correct output even if one module fails due to transient faults, permanent hardware failures, or radiation-induced errors [1]. The proposed system implements replication at the hardware level and incorporates a robust majority voter circuit to ensure continuous operation without performance degradation [2], [3]. The design is simulated and validated using digital design tools to analyze system behavior under fault-injection scenarios. Performance metrics such as reliability, error-masking capability, propagation delay, and resource utilization are examined to evaluate the effectiveness of the TMR approach. The results demonstrate that TMR significantly enhances system reliability and resilience by masking single-point failures, making it a practical solution for mission-critical applications where system downtime or incorrect outputs are unacceptable [1], [3]. This project provides a comprehensive understanding of fault-tolerant design strategies and highlights the trade-offs between hardware redundancy, system complexity, and operational reliability.

Reliability issue such as soft error due to scaling IC technology, low voltage supply and heavy thermal effects, has caused fault tolerant design be a challenge for NoC(Network-on-Chip). The router is a core element of the NoC, and the virtual channel based on flip-flop which occupies most of the area is the most sensitive element to soft error of the router. Focus on this problem, a dynamic reliable virtual channel architecture is proposed in this paper. It can detect the utilization of the virtual channel to adjust physical configuration to support for no-protection, dual redundancy and TMR (triple modular redundancy) requirements in flexibility. Compared with typical TMR virtual channel design, the synthesis results show that our method can achieve several fault tolerant structures switch with near 3 times resource utilization in ideal case and only 13.8% extra area cost.

Reduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening design flow differs from the standard design flow and currently suffers from insufficient industrial EDA tool support. R-Abax is an academic, Displacement-driven RADHARD legalisation algorithm, based on the Triple Modular Redundancy (TMR) technique, solely for Flip-Flops (FF). R-Abax ensures that a particle strike will only affect one FF of the TMR triplet, by enforcing minimum spacing constraints among FF triplets. Although the Displacement-driven R-Abax algorithm easily satisfies the spacing constraints, its Quality of Results (QoR) depends strongly on the QoR of the original placement. In this work, we propose an improved version of R-Abax, which considers the circuit Total Half-Perimeter Wire Length (HPWL) when evaluating cell moves. Experimental results indicate that the HPWL-driven R-Abax can achieve an improvement in Power, Performance and Area (PPA), compared to the Displacement-driven version. For the HPWL-driven R-Abax, as with the original version, larger minimum spacing constraints between triplet FFs does not significantly affect the QoR, rendering the proposed RADHARD flow attractive for achieving Transient Faults mitigation. © 2020 IEEE.

Triple modular redundancy (TMR) is a single-event upset (SEU)-mitigation technique that uses three circuit copies to mask a failure in any one copy. It improves the soft error reliability of designs implemented on SRAM-based field-programmable gate arrays (FPGAs) by masking the effects of upsets in the configuration memory. Although TMR is most effective when applied to an entire FPGA design, a reduction in the sensitive cross section of an FPGA design can be obtained by applying TMR selectively. This article explores several approaches for selecting components to triplicate. The benefit is a reduction in the neutron cross section for any output error as a percentage compared to that of a non-triplicated design. The cost is the percentage of components triplicated. The goal is to maximize the benefit-cost ratio. Twenty-five different selections are tested on a benchmark design. Some selections increase the cross section; others decrease the cross section significantly.

The field-programmable gate arrays (FPGAs) are widely used in varies fields in recent years. However, because of large amounts of configuration memories in FPGAs are used to implement logic and routing, the single event upset (SEU) problem makes them not feasible for applications that need high reliability. Moreover, as the threshold voltage becomes lower with the development of silicon process technology, the configuration memories are becoming more sensitive to SEU. Therefore, FPGAs require new technology to improve its dependability. In this research, we first develop a new Hamming code based error detect and correct (EDC) circuit that can prevent the configuration memory of a reconfigurable device from SEU. We then propose a novel reconfigurable logic element, namely COGRE, which will use much less configuration memory than the conventional FPGA 4-, 5- or 6-LUTs (lookup tables). Evaluation revealed that compared to the 6-LUT FPGAs with triple modular redundancy (TMR) configuration memory blocks, the 5- and 6-input COGRE with the novel error detect and correct circuit save about 75.44 and 74.29% memories on average, respectively. And the dependability of the proposed architectures is about 6.8 to 10 times better than the LUTs with a tile level TMR structure on average. Moreover, with the consideration of the on the fly scrubbing advantage of the EDC, SEUs cannot be accumulated, so a much higher dependability can be achieved.

Web search constitutes an important class of dataintensive online services in data centers. Optimizing search systems for energy efficiency, timely response and high search quality (i.e., how relevant the returned results are to a search query), however, is very challenging, as a search system involves a distributed architecture with hundreds of thousands of index serving nodes (ISNs) that return searching results to an aggregator through multiple interdependent retrieval stages in a partition-aggregate fashion. In this paper, we discover through experiments two important characteristics that can affect the system performance: (1) response time and energy consumption are greatly impacted by a small fraction of queries with long processing times; (2) the quality contribution of the ISN is independent of the query processing time. Based on our observation, we propose TailCut, which judiciously discards long query executions and enables ISN-aggregator coordination to minimize energy consumption subject to latency and quality constraints. Our experimental results show that TailCut can achieve up to 39% power saving, while satisfying the tail latency and quality constraint.

In this article, time diversity is used as an electromagnetic resilience technique in a triple modular redundant (TMR) communication channel that is subjected to a multiharmonic electromagnetic disturbance under semireverberant environments. This study is carried out in light of new electromagnetic interference (EMI) condition monitoring definitions, which provide a better insight into the actual state of the system. An explanation of the different fault mechanisms based on the new definitions is provided for a time diverse TMR system with a two-out-of-three majority voter and is compared with the previously used EMI condition monitoring definitions. The new definitions provide a better understanding on how to interpret the results of an EMI detector or an EMI corrector by keeping in consideration the safety and availability aspects of system.

Latest results of SEE measurements obtained by the STRURED demonstrator ASIC

We present a co-design approach to establish redundancy schemes such as Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR) to a whole region of a processor array for a class of Coarse-Grained Reconfigurable Arrays (CGRAs). The approach is applied to applications with mixed-criticality properties and experiencing varying Soft Error Rates (SERs) due to environmental reasons, e. g., changing altitude. The core idea is to adapt the degree of fault protection for loop programs executing in parallel on a CGRA to the level of reliability required as well as SER profiles. This is realized through claiming neighbor regions of processing elements for the execution of replicated loop nests. First, at the source code level, a compiler transformation is proposed that realizes these replication schemes in two steps: (1) replicate given parallel loop program two or three times for DMR or TMR, respectively, and (2) add appropriate error handling functions (voting or comparison) in order to detect respectively correct any single errors. Then, using the opportunities of hardware/software co-design, we propose optimized implementations of the error handling functions in software as well as in hardware. Finally, experimental results are given for the analysis of reliability gains for each proposed scheme of array replication in dependence of different SERs.

Reliability means and radiation resistance of digital equipment. For aerospace computer systems is extremely urgent to develop radiation-resistant components. One way to ensure the radiation resistance is the creation of a special architecture — RHBD (Radiation Hardened by Design). This approach includes triple redundancy (Triple Modular Redundancy — TMR) to reduce radiation-induced switching of logic elements (Single Event Transients — SET) and memory elements (Single Event Upset — SEU). FPGA due to the large number of elements configuration memory is not vulnerable to the effects of radiation. Therefore, one-time programmable devices are used, for example, the companies Actel, but flip-flops tripled too. Nevertheless, in the SRAM configurable FPGA Virtex (Xilinx) used triple redundancy with Majority Vote Circuit based on a tristate buffer instead LUT. Such Voter has implementation features that are explored in the article. One of the variants of majority voter for the pins of the FPGA using a minority voting function. Only in this case, no conflict of signals at the outputs of buffers. Describes CMOS implementation of the voters. The paper proposes a fault tolerant CMOS implementation of the Majority Voter and Minority Voter in order to improve reliability and FPGA radiation resistance.