A switched-capacitor inductance simulation circuit realized with current conveyors

This paper describes switched-capacitor (SC) inductor and Frequency Dependent Negative Resistor (FDNR) which use second generation current conveyor (CC II). In general CC II's used in SC circuits are not always used as CC II and there are phase periods in which CC II behaves as much simpler active device like unity gain buffer (UGB). In this paper, CC II's in SC circuits always behave as CC II to make full use of CC II. Then an SC inductor in which effects of parasitic capacitors can be reduced is proposed. And SC FDNR which uses CC II to get a simple circuit structure is also proposed. Both circuits are controlled by simple two-phase control clock. The spreads of capacitor values are 1. The sum of capacitor values of SC FDNR is 4. This value is the smallest reported value in SC FDNR circuits. Simulation results by SWITCAP and experimental results by discrete components are shown.

The switched capacitor (SC) circuit has been applied to analog signal processing, but few reports have been made on the application to power circuit. Recently, a report has been made on the dc‐dc converter using the SC circuit, but the circuit still has a number of problems, e.g., the loss due to the switching element or equivalent resistance of the SC circuit, the output ripple and the noise.From such a viewpoint, this paper presents first the theoretical and experimental investigations on the energy loss, energy transmission efficiency and output power of the dc‐dc converter using the basic SC circuit. Based on that result, dc‐dc converters are considered using a series‐parallel switching SC circuit with more than one capacitor. It is seen as a result that the loss due to the equivalent resistance is inevitable, even if ideal switching elements or capacitors are used in those SC circuits.As a means to cope with this problem, the dc‐dc converter using a new SC circuit is proposed, where the zero‐voltage switching mechanism is employed using a high‐frequency supply and the peak‐detector circuit. It is shown theoretically that the loss due to the equivalent resistance is not produced in principle in the proposed SC circuit. A result of experiment is shown with a drastic improvement.

The philosophy, theory and numerical techniques required in the development of a contemporary suite of simulators for switched network and mixed-mode analysis are described in detail. The evolution of a general simulator, SCNAP4, from earlier software is outlined, and comprehensive sensitivity analysis of switched capacitor (SC) and switched current (SI) networks is shown, together with full noise analysis for large SC and SI networks. An extension into semi-symbolic analysis of non-ideal SC and SI circuits is shown to be feasible, with good accuracy being maintained for large networks. The highly efficient techniques are then utilised for large signal distortion analysis and implemented in the SCNAPDIS simulator. The natural progression of the software development subsequently leads to SCNAP5, which interfaces with the commercial logic simulator Verilog to produce a most effective mixed-mode simulator capable of delivering very detailed analysis of mixed-mode SC and SI circuits. In the development of this latest suite of SCNAP software much effort has been directed towards producing highly efficient algorithms, very versatile packages and a uniform structure with a simple user interface. All the software is written in C. A variety of examples are given to illustrate the wide range of application of the software.

Surface roughness effects on electromechanical performance of RF-MEMS capacitive switches

Switched capacitor (SC) dc–dc converters are showing great potential for new applications such as data centres, electric vehicles, and power transmission. Many SC topologies have been synthesized on an ad-hoc basis, although new computer methods are being introduced to formalize this process. This article presents a general synthesis technique that can be incorporated into a computer algorithm to assist with the development of new SC circuits. The technique is based on interleaving SC converter circuits, where two unipolar converters are connected in parallel, and each leg is driven by separate, complementary gate signals. By applying this method to the traditional Ladder SC converter, a topology termed a simplified interleaved ladder (SIL) converter, is synthesized and tested using a hardware prototype. The resonant implementation of the SIL converter has desirable features for MV/LV applications when compared with other existing SC circuits.

In this paper a new voltage buffer to realize high speed and low power dissipation switched-capacitor filters is proposed. The drain-follower achieves 300MHz bandwidth with 2pF load; DC gain of 0.993V/V, 1mV offset voltage, -60 dB total harmonic distortion at 0.4 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</sub> output voltage and 58.5μW power dissipation from 1.5V supply. A unity-gain buffer switched-capacitor biquad filter has been implemented in 0.5μm CMOS technology. The circuit has been sending for fabrication. Simulation results of the biquad filter indicate operation at 100 MHz with 6mW power consumption from a 1.5 V supply can be achieved.

Chapter 7 - Advanced Switched-Capacitor Circuit Techniques

Presented in this paper is a low power, area efficient pipeline analog-to-digital converter (ADC), utilising a charge summation technique and a switched-capacitor implementation. Utilising switched capacitor, a staircase ramp is produced caused by the switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation technique is the reduction in power usage as the charging time of the capacitors is small so for most of the sample period the circuit is quiescent. The paper presents the use of this architecture as a 14-bit pipelined ADC, which can sample data at a rate of 1 MSps. The pipeline architecture itself is novel as the typical sub-DAC is not required. The signal-to-noise ratio (SNR) of the ADC is improved by using a spatial over-sampling technique, which reduces the thermal noise effect on in the switched capacitor circuit. The effects of opamps finite gain and offset on the linearity of the ramp are reduced by employing a finite gain and offset compensated integrator architecture and through the use of low-resolution pipeline stages. The proposed architecture is a strong candidate for applications demanding high resolution with low power requirements.

This paper presents a novel approach to the exact design of first- and second-order Bode-type variable-amplitude (VA) bilinear-LDI switched-capacitor (SC) equalizers. The proposed design approach is based on the realization of the VA equalizer transfer function as the transfer function of a frequency-independent two-terminal-pair SC network at its input terminal-pair when its output terminal-pair is terminated in a (frequency-dependent) SC one-terminal-pair realization of the dual of the equalizer shaping impedance function. The resulting first-order equalizers produce fan-shaped lowpass or highpass magnitude-frequency responses, while the resulting second-order equalizer produces a bump-shaped (bandpass) magnitude-frequency response. The salient feature of the proposed SC equalizers is that only a single variable capacitor is required to control the fan amplitude in the first-order equalizers and the bump amplitude in the second-order equalizer. Moreover, these equalizers remain BIBO stable for all possible values of the variable capacitor. In addition, they exhibit the important practical feature that a geometrically symmetric change in the value of the variable capacitor causes a corresponding arithmetically symmetric change in the logarithmic magnitude-frequency response of the VA equalizer. An application example is given to illustrate the main results.

A new circuit is proposed for a steep step-up of the line voltage. It integrates a switched-capacitor (SC) circuit within a boost converter. An SC circuit can achieve any voltage ratio, allowing for a boost of the input voltage to high values. It is unregulated to allow for a very high efficiency. The boost stage has a regulation purpose. It can operate at a relatively low duty cycle, thus avoiding diode-reverse recovery problems. The new circuit is not a cascade interconnection of the two power stages; their operation is integrated. The simplicity and robustness of the solution, the possibility of getting higher voltage ratios than cascading boost converters, without using transformers with all their problems, and the good overall efficiency are the benefits of the proposed converter.

Smart devices incorporating 3D hover or fingerprint sensor require a high-resolution capacitance-to-digital converter (CDC) to detect very small changes in capacitance of only tens of aF [1]. Although the switched-capacitor (SC) delta-sigma (ΔΣ) CDCs have accomplished high resolution [2], [3], the SC ΔΣ CDCs suffer from sampling noise penalty and are prone to an input parasitic capacitor (CP). In addition to the resolution, the CDCs in the systems are designed for low power consumption and small areas, considering integration in mobile devices. The current conveyor front-end is proposed in [1] and effectively isolates the CP from the following ADC, resulting in high energy efficiency. However, the work in [1] achieved a limited CP immunity (only 30pF) and is sensitive to high-frequency interference due to the limitation of SC ΔΣ CDCs. In this work, a continuous-time (CT) ΔΣ CDC, which consists of a class-AB current conveyor and a CT ΔΣ ADC, is proposed. Implemented in a small area of 0.033mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , it achieves 21.5-pF resolution with a high CP immunity of 480pF and a tolerance to high-frequency interference.

A circuit technique is proposed to reduce the capacitance spread of high-Q switched-capacitor (SC) filters, without increasing the sensitivity or requiring higher DC amplifier gain. The proposed SC integrator attenuates the input during both clock phases, so that the time constant of the integrator is realized with the product of two capacitance ratios instead of a single capacitance ratio. The capacitance spread then only increases as the square root of the time constant. The integrator is stray-insensitive. The enhancement of amplifier offset due to the proposed integrator is often negligible if the total offset of the entire SC filter is considered. A lowpass notch SC biquad is presented as an example to show the capacitance advantage of the integrator. In the numerical example, the new SC lowpass notch biquad reduces the total capacitance by a factor of more than three. >

A delta-sigma modulator (DSM) is proposed for the direct connection to micro-electro-mechanical systems (MEMS) microphone. To reduce power, both the DAC reference voltage (VREF) and the DSM supply voltage (VDD) are reduced to 700 mV by limiting the maximum linear acoustic input range to 110 dB SPL (sound pressure level). For the low VDD operation, the switched capacitor (SC) integrators of DSM employ CMOS inverters as amplifiers. A unity-gain buffer compensates the pole error of the SC integrator; it reduces chip area by replacing the auto-zero capacitor of conventional inverter-based SC integrator. Compared to the conventional integrator, the integrator of this brief reduces the pole error from 0.3% to 0.06%, reduces the chip area and the power by 32.4% and 24.8%, respectively. The 3rd order DSM in a 65 nm CMOS process was measured to have Walden-figure of merit (FoMw) 89.3fJ/step, dynamic range (DR) 90.1 dB, signal-to-noise ratio (SNR) 87.2 dB, signal-to-noise and distortion ratio (SNDR) 86.4 dB, and power 122 uW at 10 MHz clock frequency (Fs).

A DC-DC converter is one of the converters broadly used in power electronics applications and finds its place in designing of Electric Vehicles (EVs), Hybrid Electric Vehicles (HEVs), subway cars etc. A Switched Capacitor (SC) DC-DC converter consists of four switches especially MOSFET along with two capacitors that smoothens the output voltage ripples and current spikes gets reduced by the stray inductor. Furthermore, interleaving of the switched capacitor is done by connecting the circuits in series and in parallel with a certain phase displacement of 2*π/Z, where Z is the number of parallel branches and increases the voltage gain and current gain respectively. Interleaving is a technique that reduces the number of passive filter components as the branches are increased thus reducing the current stress. In this paper simulation results of high gain interleaved switched capacitor DC-DC converter are presented.

A CMOS current conveyor is proposed, and an MOSFET-capacitor integrator consisting of the CMOS current conveyor, MOSFETs biased in the triode region, capacitors, and a unity-gain buffer is presented. Based on this integrator, high-frequency integrated filters can be constructed. However, the design of such filters is complicated by the fact that the effective mobility of each device may vary and the basic building blocks (i.e. operational amplifiers or CMOS current conveyors) are not ideal. An optimization program has been developed to automate the design of this kind of filter. The program iteratively adjusts the W/L ratios and capacitance values through interfacing with SPICE to achieve the desired filtering performance. Simulation results on a six-order bandpass ladder filter with center frequency at 460 kHz, 0.5-dB ripple in the passband, and a bandwidth of 120 kHz are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>