Development of efficient switched network and mixed-mode simulators

This paper describes switched-capacitor (SC) inductor and Frequency Dependent Negative Resistor (FDNR) which use second generation current conveyor (CC II). In general CC II's used in SC circuits are not always used as CC II and there are phase periods in which CC II behaves as much simpler active device like unity gain buffer (UGB). In this paper, CC II's in SC circuits always behave as CC II to make full use of CC II. Then an SC inductor in which effects of parasitic capacitors can be reduced is proposed. And SC FDNR which uses CC II to get a simple circuit structure is also proposed. Both circuits are controlled by simple two-phase control clock. The spreads of capacitor values are 1. The sum of capacitor values of SC FDNR is 4. This value is the smallest reported value in SC FDNR circuits. Simulation results by SWITCAP and experimental results by discrete components are shown.

The switched capacitor (SC) circuit has been applied to analog signal processing, but few reports have been made on the application to power circuit. Recently, a report has been made on the dc‐dc converter using the SC circuit, but the circuit still has a number of problems, e.g., the loss due to the switching element or equivalent resistance of the SC circuit, the output ripple and the noise.From such a viewpoint, this paper presents first the theoretical and experimental investigations on the energy loss, energy transmission efficiency and output power of the dc‐dc converter using the basic SC circuit. Based on that result, dc‐dc converters are considered using a series‐parallel switching SC circuit with more than one capacitor. It is seen as a result that the loss due to the equivalent resistance is inevitable, even if ideal switching elements or capacitors are used in those SC circuits.As a means to cope with this problem, the dc‐dc converter using a new SC circuit is proposed, where the zero‐voltage switching mechanism is employed using a high‐frequency supply and the peak‐detector circuit. It is shown theoretically that the loss due to the equivalent resistance is not produced in principle in the proposed SC circuit. A result of experiment is shown with a drastic improvement.

Automatic symbolic analysis of SC networks using a modified nodal approach

The paper describes an extension of Moschytz and Brugger's signal-flow graph analysis of switched capacitor (SC) networks. The approach is based on the application of the ‘direct topological rules’ of graph theory. The method enables speedy hand analysis of general SC networks of medium complexity, and is especially effective for the analysis of passive SC circuits. To become familiar with the writing by-inspection of the driving-point and transfer functions, the first part of the paper briefly reviews the direct analysis of reciprocal networks.

Chapter 7 - Advanced Switched-Capacitor Circuit Techniques

Switched capacitor (SC) dc–dc converters are showing great potential for new applications such as data centres, electric vehicles, and power transmission. Many SC topologies have been synthesized on an ad-hoc basis, although new computer methods are being introduced to formalize this process. This article presents a general synthesis technique that can be incorporated into a computer algorithm to assist with the development of new SC circuits. The technique is based on interleaving SC converter circuits, where two unipolar converters are connected in parallel, and each leg is driven by separate, complementary gate signals. By applying this method to the traditional Ladder SC converter, a topology termed a simplified interleaved ladder (SIL) converter, is synthesized and tested using a hardware prototype. The resonant implementation of the SIL converter has desirable features for MV/LV applications when compared with other existing SC circuits.

Several methods have been developed for the analysis of circuits with periodically switched linear networks. One of the earlier works, published in the 1950s, performed the analysis of these networks using a state-space methodology based on unit complex sinusoidal step responses and unit relaxation functions, for the different switch states [1]. In the 1970s, other methods were published, using different approaches of the same methodology, which were more suitable for digital computation [2, 3]. In [4], the state-space methodology was adapted specifically for switched-capacitor (SC) circuits, which led to significant simplifications, due to the reduced number of different elements. In [5], a more computationally efficient state-space analysis method, valid for any ideal switch configuration, was presented.

The author describes a novel switched capacitor (SC) inductance simulation circuit which simulates floating inductance using a current conveyor and unity gain buffer and is controlled by a two-phase clock. The spread between capacitor values and the sum of capacitors are small and that of the whole filter using this SC inductor tends to become small. Simulation results for a third-order lowpass filter using the proposed SC inductors are presented to show that the effect of parasitic capacitors on the novel SC inductor is less than that of a previously proposed SC inductor. >

A new circuit is proposed for a steep step-up of the line voltage. It integrates a switched-capacitor (SC) circuit within a boost converter. An SC circuit can achieve any voltage ratio, allowing for a boost of the input voltage to high values. It is unregulated to allow for a very high efficiency. The boost stage has a regulation purpose. It can operate at a relatively low duty cycle, thus avoiding diode-reverse recovery problems. The new circuit is not a cascade interconnection of the two power stages; their operation is integrated. The simplicity and robustness of the solution, the possibility of getting higher voltage ratios than cascading boost converters, without using transformers with all their problems, and the good overall efficiency are the benefits of the proposed converter.

This article proposes an enhanced non-isolated high-gain DC-DC converter for interfacing renewable energy sources (RESs). This converter utilizes active switched-inductor (ASL) and switched-capacitor (SC) networks in which the ASL network increases the voltage gain. Furthermore, using the SC network as a multiplier cell helps to reach a high voltage conversion ratio with a proper duty cycle. The main advantages of the proposed converter are the high voltage gain, continuous input current, and low voltage stress on the semiconductor switch and the passive component. Since the voltage stress of the semiconductor element is low, a low ON-state resistance switch is used, which leads to reduced conduction losses. Comprehensive analysis of the steady-state operation in continuous conduction mode (CCM), inductor and capacitor design, and a comparison considering other similar topologies are presented in this article. Also, the parasitic elements are assumed to calculate the DC-Voltage gain and the efficiency of the converter. Finally, simulation results are presented in the PSIM environment to validate the feasibility of the proposed converter.

Presented in this paper is a low power, area efficient pipeline analog-to-digital converter (ADC), utilising a charge summation technique and a switched-capacitor implementation. Utilising switched capacitor, a staircase ramp is produced caused by the switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation technique is the reduction in power usage as the charging time of the capacitors is small so for most of the sample period the circuit is quiescent. The paper presents the use of this architecture as a 14-bit pipelined ADC, which can sample data at a rate of 1 MSps. The pipeline architecture itself is novel as the typical sub-DAC is not required. The signal-to-noise ratio (SNR) of the ADC is improved by using a spatial over-sampling technique, which reduces the thermal noise effect on in the switched capacitor circuit. The effects of opamps finite gain and offset on the linearity of the ramp are reduced by employing a finite gain and offset compensated integrator architecture and through the use of low-resolution pipeline stages. The proposed architecture is a strong candidate for applications demanding high resolution with low power requirements.

This paper presents a novel approach to the exact design of first- and second-order Bode-type variable-amplitude (VA) bilinear-LDI switched-capacitor (SC) equalizers. The proposed design approach is based on the realization of the VA equalizer transfer function as the transfer function of a frequency-independent two-terminal-pair SC network at its input terminal-pair when its output terminal-pair is terminated in a (frequency-dependent) SC one-terminal-pair realization of the dual of the equalizer shaping impedance function. The resulting first-order equalizers produce fan-shaped lowpass or highpass magnitude-frequency responses, while the resulting second-order equalizer produces a bump-shaped (bandpass) magnitude-frequency response. The salient feature of the proposed SC equalizers is that only a single variable capacitor is required to control the fan amplitude in the first-order equalizers and the bump amplitude in the second-order equalizer. Moreover, these equalizers remain BIBO stable for all possible values of the variable capacitor. In addition, they exhibit the important practical feature that a geometrically symmetric change in the value of the variable capacitor causes a corresponding arithmetically symmetric change in the logarithmic magnitude-frequency response of the VA equalizer. An application example is given to illustrate the main results.

The functional performance of switched capacitor circuits is directly affected by variations in capacitor ratios. We have proposed techniques to accurately measure these capacitor ratios. In this paper we develop an optimal procedure to minimize the number of capacitor ratios that need to be measured while still maintaining the desired fault coverage. We make use of the sensitivity of individual performance specifications to specific capacitor ratios. The procedure has been validated with a number of examples including a first order lossy integrator a second order low-pass filter and sixth order high Q bandpass filter. The procedure developed in this paper can easily be extended to include other switched capacitor circuits.

The two‐phase switched capacitor (SC) network containing nullators and norators as active elements has two different network structures between which it alternates periodically, Since the current and voltage graphs can be defined for each of those, the network behavior is based on four graphs. This paper considers such SC network and derives topological formulas for z‐domain network functions. SC common trees are defined first for the above pairs of current and voltage graphs, and it is shown that the denominator polynomial of the response function is represented by the sum of common‐tree‐admittance products for all SC common trees. Therefore, based on that formula, topological discussions are made on the solvability and the complexity of the network from the graph‐theoretical viewpoint. As a result, the condition for the solvability of the network and the inherent complexity of the network are derived from a topological viewpoint.

A new hybrid switched-capacitor-boost converter in which the energy is processed only once is proposed: the input ports of a switched-capacitor (SC) circuit and a boost power stage are connected in parallel whereas their output ports are connected in series. The SC converter is formed by two sub-stages which are operated with interleaving. It is unregulated. Its capacitors are charged till almost saturation, the difference between the voltages across the capacitors at the end of the charging interval and end of the discharging interval is very small, resulting in a very high efficiency of the capacitors charging process. The purpose of the SC stage is to give most of the voltage step-up gain. It processes most of the energy. Only a small portion of the energy is processed by a PWM boost converter. Its purpose is to assure overall regulation. As the role of this stage is not to step-up the voltage, it can work with a small duty-cycle value, chosen to get the highest possible efficiency. The sub-stages of the SC circuit are interleaved with the boost stage to minimize the input current ripple. As a result, a converter with high efficiency, large voltage step-up, and small input current ripple is obtained. The line and load regulation ability of the new configuration is proved analytically and confirmed experimentally. A 200 W prototype was built to step-up an input voltage of 14 V to 98 V. The measured efficiency is 87%.