Optimal test-set generation for parametric fault detection in switched capacitor filters

The switched capacitor (SC) circuit has been applied to analog signal processing, but few reports have been made on the application to power circuit. Recently, a report has been made on the dc‐dc converter using the SC circuit, but the circuit still has a number of problems, e.g., the loss due to the switching element or equivalent resistance of the SC circuit, the output ripple and the noise.From such a viewpoint, this paper presents first the theoretical and experimental investigations on the energy loss, energy transmission efficiency and output power of the dc‐dc converter using the basic SC circuit. Based on that result, dc‐dc converters are considered using a series‐parallel switching SC circuit with more than one capacitor. It is seen as a result that the loss due to the equivalent resistance is inevitable, even if ideal switching elements or capacitors are used in those SC circuits.As a means to cope with this problem, the dc‐dc converter using a new SC circuit is proposed, where the zero‐voltage switching mechanism is employed using a high‐frequency supply and the peak‐detector circuit. It is shown theoretically that the loss due to the equivalent resistance is not produced in principle in the proposed SC circuit. A result of experiment is shown with a drastic improvement.

This paper describes switched-capacitor (SC) inductor and Frequency Dependent Negative Resistor (FDNR) which use second generation current conveyor (CC II). In general CC II's used in SC circuits are not always used as CC II and there are phase periods in which CC II behaves as much simpler active device like unity gain buffer (UGB). In this paper, CC II's in SC circuits always behave as CC II to make full use of CC II. Then an SC inductor in which effects of parasitic capacitors can be reduced is proposed. And SC FDNR which uses CC II to get a simple circuit structure is also proposed. Both circuits are controlled by simple two-phase control clock. The spreads of capacitor values are 1. The sum of capacitor values of SC FDNR is 4. This value is the smallest reported value in SC FDNR circuits. Simulation results by SWITCAP and experimental results by discrete components are shown.

An approximate measure for the noise performance of integrator-based SC (switched capacitor) filters of general order n is developed. The measure is dependent on SC-design parameters such as capacitor ratios and capacitance levels, but not on technology-dependent parameters describing the switches and amplifiers. A simple and explicit closed-form expression for this approximate noise measure is derived and compared with more complex-and accurate-measures. The comparison demonstrates extraordinary accuracy for the approximate noise computation presented. An important application for this noise measure is in the optimization of integrator-based SC filters; it is used in the computer-aided design of sensitivity- and noise-optimized SC filters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A circuit technique is proposed to reduce the capacitance spread of high-Q switched-capacitor (SC) filters, without increasing the sensitivity or requiring higher DC amplifier gain. The proposed SC integrator attenuates the input during both clock phases, so that the time constant of the integrator is realized with the product of two capacitance ratios instead of a single capacitance ratio. The capacitance spread then only increases as the square root of the time constant. The integrator is stray-insensitive. The enhancement of amplifier offset due to the proposed integrator is often negligible if the total offset of the entire SC filter is considered. A lowpass notch SC biquad is presented as an example to show the capacitance advantage of the integrator. In the numerical example, the new SC lowpass notch biquad reduces the total capacitance by a factor of more than three. >

Theoretical and graphical analysis of pull-in-voltage and figure of merit for a fixed-fixed capacitive Micro Electromechanical Systems (MEMS) switch is presented in this paper. MEMS switch consists of a thin electrode called bridge suspended over a central line and both ends of the bridge are fixed at the ground planes of a coplanar waveguide (CPW) structure. A thin layer of dielectric material is deposited between the bridge and centre conductor to avoid stiction and provide low impedance path between the electrodes. When an actuation voltage is applied between the electrodes, the metal bridge acquires pull in effect as it crosses one third of distance between them. In this study, we describe behavior of pull-in voltage and figure of merit (or capacitance ratio) of capacitive MEMS switch for five different dielectric materials. The effects of dielectric thicknesses are also considered to calculate the values of pull-in-voltage and capacitance ratio. This work shows that a reduced pull-in-voltage with increase in capacitance ratio can be achieved by using dielectric material of high dielectric constant above the central line of CPW.

Chapter 7 - Advanced Switched-Capacitor Circuit Techniques

The philosophy, theory and numerical techniques required in the development of a contemporary suite of simulators for switched network and mixed-mode analysis are described in detail. The evolution of a general simulator, SCNAP4, from earlier software is outlined, and comprehensive sensitivity analysis of switched capacitor (SC) and switched current (SI) networks is shown, together with full noise analysis for large SC and SI networks. An extension into semi-symbolic analysis of non-ideal SC and SI circuits is shown to be feasible, with good accuracy being maintained for large networks. The highly efficient techniques are then utilised for large signal distortion analysis and implemented in the SCNAPDIS simulator. The natural progression of the software development subsequently leads to SCNAP5, which interfaces with the commercial logic simulator Verilog to produce a most effective mixed-mode simulator capable of delivering very detailed analysis of mixed-mode SC and SI circuits. In the development of this latest suite of SCNAP software much effort has been directed towards producing highly efficient algorithms, very versatile packages and a uniform structure with a simple user interface. All the software is written in C. A variety of examples are given to illustrate the wide range of application of the software.

A new circuit is proposed for a steep step-up of the line voltage. It integrates a switched-capacitor (SC) circuit within a boost converter. An SC circuit can achieve any voltage ratio, allowing for a boost of the input voltage to high values. It is unregulated to allow for a very high efficiency. The boost stage has a regulation purpose. It can operate at a relatively low duty cycle, thus avoiding diode-reverse recovery problems. The new circuit is not a cascade interconnection of the two power stages; their operation is integrated. The simplicity and robustness of the solution, the possibility of getting higher voltage ratios than cascading boost converters, without using transformers with all their problems, and the good overall efficiency are the benefits of the proposed converter.

Switched capacitor (SC) dc–dc converters are showing great potential for new applications such as data centres, electric vehicles, and power transmission. Many SC topologies have been synthesized on an ad-hoc basis, although new computer methods are being introduced to formalize this process. This article presents a general synthesis technique that can be incorporated into a computer algorithm to assist with the development of new SC circuits. The technique is based on interleaving SC converter circuits, where two unipolar converters are connected in parallel, and each leg is driven by separate, complementary gate signals. By applying this method to the traditional Ladder SC converter, a topology termed a simplified interleaved ladder (SIL) converter, is synthesized and tested using a hardware prototype. The resonant implementation of the SIL converter has desirable features for MV/LV applications when compared with other existing SC circuits.

Presented in this paper is a low power, area efficient pipeline analog-to-digital converter (ADC), utilising a charge summation technique and a switched-capacitor implementation. Utilising switched capacitor, a staircase ramp is produced caused by the switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation technique is the reduction in power usage as the charging time of the capacitors is small so for most of the sample period the circuit is quiescent. The paper presents the use of this architecture as a 14-bit pipelined ADC, which can sample data at a rate of 1 MSps. The pipeline architecture itself is novel as the typical sub-DAC is not required. The signal-to-noise ratio (SNR) of the ADC is improved by using a spatial over-sampling technique, which reduces the thermal noise effect on in the switched capacitor circuit. The effects of opamps finite gain and offset on the linearity of the ramp are reduced by employing a finite gain and offset compensated integrator architecture and through the use of low-resolution pipeline stages. The proposed architecture is a strong candidate for applications demanding high resolution with low power requirements.

The author describes a novel switched capacitor (SC) inductance simulation circuit which simulates floating inductance using a current conveyor and unity gain buffer and is controlled by a two-phase clock. The spread between capacitor values and the sum of capacitors are small and that of the whole filter using this SC inductor tends to become small. Simulation results for a third-order lowpass filter using the proposed SC inductors are presented to show that the effect of parasitic capacitors on the novel SC inductor is less than that of a previously proposed SC inductor. >

Switched capacitor (SC) circuits are derived (designed) from passive LC ladders, RC-active circuits or digital structures. This paper reviews the different design techniques of SC-circuits and concentrates on those derived from digital structures. Also, the paper demonstrates various signal processing applications using SC-circuits.

A novel approach for the realization of switched-capacitor decimation filters is proposed. The design process is based on the optimum allocation of poles and zeros of a transfer function, so that the best compromise is achieved between filter complexity and sensitivity with respect to capacitance ratio errors. Analytical boundaries enclosing the feasible frequency responses for a given nominal design and specified capacitance ratio tolerance are used, enabling quick and reliable statistical sensitivity comparisons without the need for Monte Carlo simulations. Results are shown for an illustrative design example of a video-frequency decimation filter. A prototype filter has been built and tested in the laboratory to validate the theory, and measurement results are included.

RF MEMS capacitive switch on semi-suspended CPW using low-loss high-resistivity silicon substrate

Although the circuit in the conventional switched capacitor (SC) current source (SCCS) is extremely simple, the output current ripple incresaes if the input frequency is reduced. This paper proposes a new reduced ripple SC current source (RRSCCS) in which an integrator circuit is added to the conventional circuit to reduce the ripple. The output current from the proposed circuit can be determined by the voltage, frequency and capacitance as in the conventional circuit. In addition, no current ripple occurs theoretically in the new circuit. As examples of applications, a frequency‐controlled voltage source (FCVS) and a current source proportional to the square of the frequency (F2CCS) are constructed. In the present FCVS, the output voltage can be made proportional to or inversely proportional to the frequency depending on the input frequency and the control frequency. Since the output voltage is determined by the capacitance ratio, frequency ratio and voltage, it is of high precision. Next, it is shown that the present F2CCS is useful for linear control of gm of the MOS‐type OTA. Good results have been obtained by experiments using individual components.