Switched capacitor circuits and their applications, an overview

The switched capacitor (SC) circuit has been applied to analog signal processing, but few reports have been made on the application to power circuit. Recently, a report has been made on the dc‐dc converter using the SC circuit, but the circuit still has a number of problems, e.g., the loss due to the switching element or equivalent resistance of the SC circuit, the output ripple and the noise.From such a viewpoint, this paper presents first the theoretical and experimental investigations on the energy loss, energy transmission efficiency and output power of the dc‐dc converter using the basic SC circuit. Based on that result, dc‐dc converters are considered using a series‐parallel switching SC circuit with more than one capacitor. It is seen as a result that the loss due to the equivalent resistance is inevitable, even if ideal switching elements or capacitors are used in those SC circuits.As a means to cope with this problem, the dc‐dc converter using a new SC circuit is proposed, where the zero‐voltage switching mechanism is employed using a high‐frequency supply and the peak‐detector circuit. It is shown theoretically that the loss due to the equivalent resistance is not produced in principle in the proposed SC circuit. A result of experiment is shown with a drastic improvement.

This paper describes switched-capacitor (SC) inductor and Frequency Dependent Negative Resistor (FDNR) which use second generation current conveyor (CC II). In general CC II's used in SC circuits are not always used as CC II and there are phase periods in which CC II behaves as much simpler active device like unity gain buffer (UGB). In this paper, CC II's in SC circuits always behave as CC II to make full use of CC II. Then an SC inductor in which effects of parasitic capacitors can be reduced is proposed. And SC FDNR which uses CC II to get a simple circuit structure is also proposed. Both circuits are controlled by simple two-phase control clock. The spreads of capacitor values are 1. The sum of capacitor values of SC FDNR is 4. This value is the smallest reported value in SC FDNR circuits. Simulation results by SWITCAP and experimental results by discrete components are shown.

Chapter 7 - Advanced Switched-Capacitor Circuit Techniques

A new circuit is proposed for a steep step-up of the line voltage. It integrates a switched-capacitor (SC) circuit within a boost converter. An SC circuit can achieve any voltage ratio, allowing for a boost of the input voltage to high values. It is unregulated to allow for a very high efficiency. The boost stage has a regulation purpose. It can operate at a relatively low duty cycle, thus avoiding diode-reverse recovery problems. The new circuit is not a cascade interconnection of the two power stages; their operation is integrated. The simplicity and robustness of the solution, the possibility of getting higher voltage ratios than cascading boost converters, without using transformers with all their problems, and the good overall efficiency are the benefits of the proposed converter.

The philosophy, theory and numerical techniques required in the development of a contemporary suite of simulators for switched network and mixed-mode analysis are described in detail. The evolution of a general simulator, SCNAP4, from earlier software is outlined, and comprehensive sensitivity analysis of switched capacitor (SC) and switched current (SI) networks is shown, together with full noise analysis for large SC and SI networks. An extension into semi-symbolic analysis of non-ideal SC and SI circuits is shown to be feasible, with good accuracy being maintained for large networks. The highly efficient techniques are then utilised for large signal distortion analysis and implemented in the SCNAPDIS simulator. The natural progression of the software development subsequently leads to SCNAP5, which interfaces with the commercial logic simulator Verilog to produce a most effective mixed-mode simulator capable of delivering very detailed analysis of mixed-mode SC and SI circuits. In the development of this latest suite of SCNAP software much effort has been directed towards producing highly efficient algorithms, very versatile packages and a uniform structure with a simple user interface. All the software is written in C. A variety of examples are given to illustrate the wide range of application of the software.

Presented in this paper is a low power, area efficient pipeline analog-to-digital converter (ADC), utilising a charge summation technique and a switched-capacitor implementation. Utilising switched capacitor, a staircase ramp is produced caused by the switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation technique is the reduction in power usage as the charging time of the capacitors is small so for most of the sample period the circuit is quiescent. The paper presents the use of this architecture as a 14-bit pipelined ADC, which can sample data at a rate of 1 MSps. The pipeline architecture itself is novel as the typical sub-DAC is not required. The signal-to-noise ratio (SNR) of the ADC is improved by using a spatial over-sampling technique, which reduces the thermal noise effect on in the switched capacitor circuit. The effects of opamps finite gain and offset on the linearity of the ramp are reduced by employing a finite gain and offset compensated integrator architecture and through the use of low-resolution pipeline stages. The proposed architecture is a strong candidate for applications demanding high resolution with low power requirements.

Switched capacitor (SC) dc–dc converters are showing great potential for new applications such as data centres, electric vehicles, and power transmission. Many SC topologies have been synthesized on an ad-hoc basis, although new computer methods are being introduced to formalize this process. This article presents a general synthesis technique that can be incorporated into a computer algorithm to assist with the development of new SC circuits. The technique is based on interleaving SC converter circuits, where two unipolar converters are connected in parallel, and each leg is driven by separate, complementary gate signals. By applying this method to the traditional Ladder SC converter, a topology termed a simplified interleaved ladder (SIL) converter, is synthesized and tested using a hardware prototype. The resonant implementation of the SIL converter has desirable features for MV/LV applications when compared with other existing SC circuits.

Multiplication is an important fundamental function in arithmetic operations. Multiplication-based operations such as Multiply and Accumulate(MAC) and inner product are among some of the frequently used computation Intensive Arithmetic Functions(CIAF) currently implemented in many Digital Signal Processing (DSP) applications such as convolution, Fast Fourier Transform(FFT), filtering and in microprocessors m its arithmetic and logic unit. Since multiplication dominates the execution tune of most DSP algorithms, so there is a need of high speed multiplier. Currently, multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. The demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications . One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier. Employing this technique in the computation algorithms will reduce the complexity, execution time, power etc. This vedic based multiplier is compared with binary multiplier(partial products method).

The functional performance of switched capacitor circuits is directly affected by variations in capacitor ratios. We have proposed techniques to accurately measure these capacitor ratios. In this paper we develop an optimal procedure to minimize the number of capacitor ratios that need to be measured while still maintaining the desired fault coverage. We make use of the sensitivity of individual performance specifications to specific capacitor ratios. The procedure has been validated with a number of examples including a first order lossy integrator a second order low-pass filter and sixth order high Q bandpass filter. The procedure developed in this paper can easily be extended to include other switched capacitor circuits.

The author describes a novel switched capacitor (SC) inductance simulation circuit which simulates floating inductance using a current conveyor and unity gain buffer and is controlled by a two-phase clock. The spread between capacitor values and the sum of capacitors are small and that of the whole filter using this SC inductor tends to become small. Simulation results for a third-order lowpass filter using the proposed SC inductors are presented to show that the effect of parasitic capacitors on the novel SC inductor is less than that of a previously proposed SC inductor. >

This paper describes the modeling and simulation of switched capacitor circuits in AWEswit. AWEswit is a mixed signal simulator for switched capacitor circuits. It allows for portions of the circuit to be modeled with digital blocks controlled by an event queue. The remainder of the circuit is modeled in the analog domain. The paper describes the circuit formulations employed by AWEswit, and how they are exploited in modeling the nonidealities associated with switched capacitor circuits. AWEswit employs asymptotic waveform evaluation (AWE) as its core simulation engine. It combines circuit formulations in the charge-voltage and current-voltage regimes. This flexibility in the circuit formulations means that if the circuit is modeled entirely with ideal switches (i.e. no resistors), then it is automatically solved in the charge-voltage regime (like SWITCAP2). However, if portions of the circuit need to be solved in the current-voltage regime, then AWEswit automatically partitions the circuit and solves the different partitions in whichever regime is appropriate, i.e., in the current-voltage regime (using AWE to evaluate circuit response) or in the charge-voltage regime. AWEswit naturally handles the bandwidth limitations associated with switched capacitor circuits. In addition, it models the clock feedthrough and signal-dependent charge dump that characterize MOSFET switches. The simulator is illustrated by example.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new hybrid switched-capacitor-boost converter in which the energy is processed only once is proposed: the input ports of a switched-capacitor (SC) circuit and a boost power stage are connected in parallel whereas their output ports are connected in series. The SC converter is formed by two sub-stages which are operated with interleaving. It is unregulated. Its capacitors are charged till almost saturation, the difference between the voltages across the capacitors at the end of the charging interval and end of the discharging interval is very small, resulting in a very high efficiency of the capacitors charging process. The purpose of the SC stage is to give most of the voltage step-up gain. It processes most of the energy. Only a small portion of the energy is processed by a PWM boost converter. Its purpose is to assure overall regulation. As the role of this stage is not to step-up the voltage, it can work with a small duty-cycle value, chosen to get the highest possible efficiency. The sub-stages of the SC circuit are interleaved with the boost stage to minimize the input current ripple. As a result, a converter with high efficiency, large voltage step-up, and small input current ripple is obtained. The line and load regulation ability of the new configuration is proved analytically and confirmed experimentally. A 200 W prototype was built to step-up an input voltage of 14 V to 98 V. The measured efficiency is 87%.

Multi‐dimensional Discrete Fourier Transforms (DFTs) play an important role in signal and image processing applications. Image reconstruction is a key component in signal processing applications like medical imaging, computer vision, face recognition etc. Two dimensional fast Fourier Transform (2D FFT) and Inverse FFT plays vital role in reconstruction. In this paper we present a fast 64 × 64 point 2D FFT architecture based on radix‐43 algorithm using a parallel unrolled radix‐4 3 FFT as the basic block. Our radix‐4 3 architecture is a memory optimized parallel architecture which computes 64‐point FFT, with least execution time. Proposed architecture produces reordered output of both 64‐point one dimensional (1D) FFT and 64 × 64 point 2D FFT, without using any additional hardware for reordering. The proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz and area of 0.841 mm 2 . The power consumption of proposed architecture is 358 mW at 500 MHz. Energy efficiency (FFTs computed per unit of energy) is 341 points/Joule. Computation time of 64 × 64 point FFT is 8.19 μs. ASIC implementation results shows better performance of proposed work in terms of computation time when compared with state‐of‐art implementation. Proposed architecture has also been implemented in Virtex‐7 FPGA which gives comparable area.

The paper describes an extension of Moschytz and Brugger&apos;s signal-flow graph analysis of switched capacitor (SC) networks. The approach is based on the application of the ‘direct topological rules’ of graph theory. The method enables speedy hand analysis of general SC networks of medium complexity, and is especially effective for the analysis of passive SC circuits. To become familiar with the writing by-inspection of the driving-point and transfer functions, the first part of the paper briefly reviews the direct analysis of reciprocal networks.

Several methods have been developed for the analysis of circuits with periodically switched linear networks. One of the earlier works, published in the 1950s, performed the analysis of these networks using a state-space methodology based on unit complex sinusoidal step responses and unit relaxation functions, for the different switch states [1]. In the 1970s, other methods were published, using different approaches of the same methodology, which were more suitable for digital computation [2, 3]. In [4], the state-space methodology was adapted specifically for switched-capacitor (SC) circuits, which led to significant simplifications, due to the reduced number of different elements. In [5], a more computationally efficient state-space analysis method, valid for any ideal switch configuration, was presented.