Automatic symbolic analysis of SC networks using a modified nodal approach

The philosophy, theory and numerical techniques required in the development of a contemporary suite of simulators for switched network and mixed-mode analysis are described in detail. The evolution of a general simulator, SCNAP4, from earlier software is outlined, and comprehensive sensitivity analysis of switched capacitor (SC) and switched current (SI) networks is shown, together with full noise analysis for large SC and SI networks. An extension into semi-symbolic analysis of non-ideal SC and SI circuits is shown to be feasible, with good accuracy being maintained for large networks. The highly efficient techniques are then utilised for large signal distortion analysis and implemented in the SCNAPDIS simulator. The natural progression of the software development subsequently leads to SCNAP5, which interfaces with the commercial logic simulator Verilog to produce a most effective mixed-mode simulator capable of delivering very detailed analysis of mixed-mode SC and SI circuits. In the development of this latest suite of SCNAP software much effort has been directed towards producing highly efficient algorithms, very versatile packages and a uniform structure with a simple user interface. All the software is written in C. A variety of examples are given to illustrate the wide range of application of the software.

The paper describes an extension of Moschytz and Brugger's signal-flow graph analysis of switched capacitor (SC) networks. The approach is based on the application of the ‘direct topological rules’ of graph theory. The method enables speedy hand analysis of general SC networks of medium complexity, and is especially effective for the analysis of passive SC circuits. To become familiar with the writing by-inspection of the driving-point and transfer functions, the first part of the paper briefly reviews the direct analysis of reciprocal networks.

This paper describes switched-capacitor (SC) inductor and Frequency Dependent Negative Resistor (FDNR) which use second generation current conveyor (CC II). In general CC II's used in SC circuits are not always used as CC II and there are phase periods in which CC II behaves as much simpler active device like unity gain buffer (UGB). In this paper, CC II's in SC circuits always behave as CC II to make full use of CC II. Then an SC inductor in which effects of parasitic capacitors can be reduced is proposed. And SC FDNR which uses CC II to get a simple circuit structure is also proposed. Both circuits are controlled by simple two-phase control clock. The spreads of capacitor values are 1. The sum of capacitor values of SC FDNR is 4. This value is the smallest reported value in SC FDNR circuits. Simulation results by SWITCAP and experimental results by discrete components are shown.

The switched capacitor (SC) circuit has been applied to analog signal processing, but few reports have been made on the application to power circuit. Recently, a report has been made on the dc‐dc converter using the SC circuit, but the circuit still has a number of problems, e.g., the loss due to the switching element or equivalent resistance of the SC circuit, the output ripple and the noise.From such a viewpoint, this paper presents first the theoretical and experimental investigations on the energy loss, energy transmission efficiency and output power of the dc‐dc converter using the basic SC circuit. Based on that result, dc‐dc converters are considered using a series‐parallel switching SC circuit with more than one capacitor. It is seen as a result that the loss due to the equivalent resistance is inevitable, even if ideal switching elements or capacitors are used in those SC circuits.As a means to cope with this problem, the dc‐dc converter using a new SC circuit is proposed, where the zero‐voltage switching mechanism is employed using a high‐frequency supply and the peak‐detector circuit. It is shown theoretically that the loss due to the equivalent resistance is not produced in principle in the proposed SC circuit. A result of experiment is shown with a drastic improvement.

A method of analyzing switched-capacitor (SC) filters which incorporates a single-pole model of the operational amplifiers (op amp's) is presented. Closed-form algebraic expressions for filter transfer functions in the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">z</tex> -domain are obtained which are computationally more efficient than time-domain methods. The necessity for including a frequency dependent model of the op amp rather than the common finite gain model in doing a performance analysis, especially when considering stability, is emphasized. To illustrate the method of analysis, an analog integrator, an analog second-order bandpass filter, and their SC counterparts are considered. The <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</tex> -domain performance of the analog \footnote[1]{circuits} is compared with the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">z</tex> -domain performance of the sampled-data configurations to show how the finite gain-bandwidth product (GB) of the op amp's affects the respective topologies. These comparisons show that the effects of switching rates and switching arrangements on filter performance are strongly dependent upon the GB product of the op amps. These comparisons also emphasize the fact that it is not sufficient to investigate the effect of the operational amplifiers on the performance of an analog filter to predict the performance of a SC filter derived from the analog configuration.

This article proposes an enhanced non-isolated high-gain DC-DC converter for interfacing renewable energy sources (RESs). This converter utilizes active switched-inductor (ASL) and switched-capacitor (SC) networks in which the ASL network increases the voltage gain. Furthermore, using the SC network as a multiplier cell helps to reach a high voltage conversion ratio with a proper duty cycle. The main advantages of the proposed converter are the high voltage gain, continuous input current, and low voltage stress on the semiconductor switch and the passive component. Since the voltage stress of the semiconductor element is low, a low ON-state resistance switch is used, which leads to reduced conduction losses. Comprehensive analysis of the steady-state operation in continuous conduction mode (CCM), inductor and capacitor design, and a comparison considering other similar topologies are presented in this article. Also, the parasitic elements are assumed to calculate the DC-Voltage gain and the efficiency of the converter. Finally, simulation results are presented in the PSIM environment to validate the feasibility of the proposed converter.

In this paper, we present a new method of analysis of switched-capacitor networks (SCN) based on the concept of capacitorswitch (CS) blocks. The combination of any capacitor and its related switches in the SCN is considered as an integral component and the nodes within the combination can be discarded. The size of the admittance matrix is thus great reduced. By this method the time- and frequency-domain responses can be computed efficiently with no limitations on the circuit topology, switching phase, or duty cycle.

In this paper we present the first switched-capacitor (SC) circuit implementation of an N-path decimating filter which has the ability to perform downconversion simultaneous with high filtering while enabling the use of operational amplifiers with relaxed specifications when compared with the traditional SC N-path filters. The example given is of a 4-path system using high-pass decimating filters with input and output sampling frequency of 40 MHz and 13.3 MHz, respectively, yielding an overall input sampling frequency of 160 MHz and thus extended input baseband from 0 to 80 MHz. The detailed simulation analysis of the circuit illustrates the resulting frequency downconversion from 60 MHz to 6.6 MHz as well as the effect of various sources of errors, e.g., operational amplifier offset and gain errors, capacitance mismatch and clock skew, in the overall baseband response and image rejection performance.

An analysis technique is proposed which takes into account the effect of finite DC gain and the gain-bandwidth product of operational amplifiers (OAs) on the response of switched-capacitor (SC) networks operated by a biphase or a multiphase clock. The general matrix equation of the network in the z-domain is split into two subsets: external charge conservation equations (CCEs), which are set up for the passive part of the network, and internal CCEs, based on equivalent OA representations. The technique is simple, versatile, applicable to SC networks of any topology and suitable for creating a computeraided analysis system. Examples are given for both to confirm the advantages of equivalent OA representations and to illustrate the technique's efficiency.

The paper presents an improvement of sensitivity analysis methods of analog lumped circuits. A practical and reliable approach has been developed and implemented in a computation program intended for linear and/or piecewise-linear approximation of the nonlinear RLCM circuits containing any type of passive elements, independent and controlled sources. A powerful modified nodal approach to build the mathematical model combined with some symbolic computation strategies has been exploited, in order to reduce the computational effort and to minimize the numerical errors. The developed software tool is conceived as a useful and valuable support for research and design engineers.

A circuit simulator has been developed on basis of Unified Nodal Analysis (UNA). It outperforms simulators with Modified Nodal Approach and Tableau formulation in that the initial-state and steady-state responses are generated from the UNA equations without transient analysis and transient simulations can be carried out from the UNA equations even for circuits with capacitor loops and inductor cutsets that cause singularity in the MNA equations. UNA's efficiency and accuracy are illustrated with an example circuit that fails most of the existing circuit simulators.

This paper considers the implementation of non-recursive switched-capacitor filters realized in transversal form for narrowband signal processing applications. Effects of random capacitance errors and finite gain and bandwidth of the operational amplifiers in the filter frequency response are investigated. Computer simulations are presented to verify the main theoretical results.

This paper presents a novel approach to the exact design of first- and second-order Bode-type variable-amplitude (VA) bilinear-LDI switched-capacitor (SC) equalizers. The proposed design approach is based on the realization of the VA equalizer transfer function as the transfer function of a frequency-independent two-terminal-pair SC network at its input terminal-pair when its output terminal-pair is terminated in a (frequency-dependent) SC one-terminal-pair realization of the dual of the equalizer shaping impedance function. The resulting first-order equalizers produce fan-shaped lowpass or highpass magnitude-frequency responses, while the resulting second-order equalizer produces a bump-shaped (bandpass) magnitude-frequency response. The salient feature of the proposed SC equalizers is that only a single variable capacitor is required to control the fan amplitude in the first-order equalizers and the bump amplitude in the second-order equalizer. Moreover, these equalizers remain BIBO stable for all possible values of the variable capacitor. In addition, they exhibit the important practical feature that a geometrically symmetric change in the value of the variable capacitor causes a corresponding arithmetically symmetric change in the logarithmic magnitude-frequency response of the VA equalizer. An application example is given to illustrate the main results.

The two‐phase switched capacitor (SC) network containing nullators and norators as active elements has two different network structures between which it alternates periodically, Since the current and voltage graphs can be defined for each of those, the network behavior is based on four graphs. This paper considers such SC network and derives topological formulas for z‐domain network functions. SC common trees are defined first for the above pairs of current and voltage graphs, and it is shown that the denominator polynomial of the response function is represented by the sum of common‐tree‐admittance products for all SC common trees. Therefore, based on that formula, topological discussions are made on the solvability and the complexity of the network from the graph‐theoretical viewpoint. As a result, the condition for the solvability of the network and the inherent complexity of the network are derived from a topological viewpoint.

Switched capacitor network has been widely used in power electronic circuits. Under the same input voltage and switch duty cycle, buck-boost converter with switched capacitor network can achieve better voltage-drop effect. Based on peak current controlled buck-boost converter with switched capacitor network, a model of discrete iterative mapping, this paper studies the entropy characteristics to analyze the nonlinear dynamic behavior of the converter. First, two-dimensional entropy of the converter is obtained, which reflects the overall statistical characteristics. Then, the numerical sequence distributions of buck-boost converter with switching capacitor network are also analyzed under different load resistors. Finally, the nonlinear dynamical analysis for the converter is verified by experimental results.