A Test Response Compression Method for Monolithic 3-D ICs Based on 3-D Haar Wavelet Transforms

Despite the benefits of data mining in a wide range of applications, this technique has raised some issues related to privacy and security of individuals. Due to these issues, data owners may prevent to share their sensitive information with data miners. In this paper, we introduce a novel approach for privacy preserving clustering (PPC) over centralized data. The proposed technique uses Haar wavelet transform (HWT) and scaling data perturbation (SDP) to protect the underlying numerical attribute values subjected to clustering analysis. In addition, some experimental results are presented, which demonstrate that the proposed technique is effective and finds an optimum in the tradeoff between clustering utility and data privacy.

With the rapid growth of technology and the proliferation of data in this digital age, current image and audio applications require greater resolution, higher data transmission rates and better data compression techniques to meet the ever increasing demands placed on them. The research presented here investigates the impact of data compression in the automatic recognition of handwritten digit images and spoken digit audio. A Haar wavelet transform (HWT) is used to compress the original image and audio data, which is input to an artificial neural network (ANN) where the automatic digit recognition is performed. The HWT generates a signature, or fingerprint, for the data by removing redundant data using a cut-off function, a number of which are investigated. This reduced data signature enables the ANN-based recogniser to be simplified and computationally more efficient. Experimental results show that for handwritten digit images, the recognition accuracy is 94.3% with compression ratios of 80%; for spoken audio digits, the recognition accuracy is 98.8% with compression ratios of 82%.

Through transmission lines (TLs), an electric power transmission system has been able to transmit power from generating stations to consumers. During transmission, various kinds of malfunctions take place and they are termed as a fault. Although fault is undesirable, it is unavoidable event hampering the smooth functioning of the power system. In power transmission systems, and a large number of voltage and current signal, distortions take place due to faults. Faults occur in power TL causing power supply interruption. Several fault detection techniques have been presented by researchers to detect a fault in TL. However, the time required to locate the fault remained higher and the power loss rate (PLR) was not reduced. To overcome these issues and identify faults in electrical power TL, Haar wavelet feature extraction-based firefly optimized fault detection (HWFE-FFOFD) method has been introduced. The power TL signal sample has been taken as an input. Zero-mean normalization is the pre-processing approach that converts the transmission signal sample into a specified range. To extort features (i.e. voltages and current values) with higher accuracy, the normalized signal has been given to Haar Wavelet Transform. Then, the extracted features at different time instants have been given to the firefly optimized fault detection (FFOFD) algorithm. In the FFOFD algorithm, extracted features have been considered as firefly populations. The FFOFD algorithm functions with the flashing behavior of a firefly. At last, the firefly position has been updated and ranked according to light intensity to detect a fault in electrical power TL. In this manner, the fault detection time (FDT) gets reduced using HWFE-FFOFD method. HWFE-FFOFD method is evaluated in FEA, FDT, and PLR. From the experimental results obtained, it can be confirmed that the HWFE-FFOFD method has been able to enhance accuracy by 14% and minimize time by 26% and PLR by 62% when compared to conventional methods.

Discrete Wavelet Transform, (DWT), is known to be one of the best compression techniques. It provides a mathematical way of encoding information in such a way that it is layered according to level of detail. In this paper, we used Haar wavelets as the basis of transformation functions. Haar wavelet transformation is composed of a sequence of low pass and high pass filters, known as filter bank. The redundancy of the DWT detail coefficients are reduced through thresholding and further through Huffman encoding. The proposed threshold algorithm is based upon the statistics of the DWT coefficients. The quality of the compressed images has been evaluated using some factors like Compression Ratio, (CR), and Peak Signal to Noise Ratio, (PSNR). Experimental results demonstrate that the proposed technique provides sufficient higher compression ratio compared to other compression thresholding techniques.

In recent years information hiding has got much attention as it acts as an alternate option for secured communication. The Secret content would get imbedded with the image using various possible image embodiment techniques, in which the Least Significant Bit (LSB) substitution is one of the preferred content embodiment strategy; however, asserting the quality and the originality of the content embedded image (stego) is yet a grievous concern in the field of Information Security. In this article, a proficient Scrambling Based Haar Wavelet Transform (SBHWT) approach has been sought to ensure the novelty of the stego-image that supports the safe transfer of data over the channel. In this process, the image is scrambled using a Sudoku pattern, and then streams of the secret content are embedded into the image blocks based on the proposals of the Bishop Traversal logic of chess. The content embodiment is attempted using normal LSB substitution and DNA pattern based substitution. Next, the image is descrambled to recover the original image, which is then subjected to Haar wavelet transformation for image resolution reduction. The resultant reduced image is channelized to the recipient and the inverse action of the SBHWT is made in order to get back the secret code stream. The experimental results demonstrate that the projected SBHWT approach is less predictable and exclusive in its pattern.

In this paper, we propose a new test data compression method for reducing test data volume and test application time. The proposed method consists of two steps: scan chain compaction and dictionary-based compression scheme. The scan chain compaction provides a minimum scan chain depth by using compaction of the compatible scan cells in the scan chain. The compacted scan chain is partitioned to the multiple internal scan chains for using the fixed-length index dictionary-based compression scheme that provides the high compression ratio and the fast testing time. The proposed compression method delivers compressed patterns from the ATE to the chip and drives a large number of multiple internal scan chains using only a single ATE input and output. Experimental results for the ISCAS-89 test benches show that the test data volume and testing time for the proposed method are less than previous compression schemes.

The rapid growing trend of utilization of re-useable intellectual property (IP) cores for system-on-chip (SOC) design demands an effective, fast and efficient test scheme. This paper presents a unified approach to SOC testing that uses a built-in self-test (BIST) technique based on summations of cores' test output voltages (SOCTOV), which has the advantage of small hardware overhead and fast testing time. The proposed BIST technique is developed in conjunction with our previous proposed BIST technique which is based on weighted sums of selected node voltages (WSSNV) for embedded cores. The WSSNV BIST technique provides high fault coverage for individual cores while the SOCTOV BIST technique provides a 100% fault diagnosis resolution for locating the faulty core. It is an alternative solution to SOC testing especially when chip area overhead is a critical concern.

With the growing complexity of integrated circuits (ICs), more and more test items are required in testing. However, the large number of invalid items (which narrowly pass the test) continues to increase the test time and, consequently, test costs. Aiming to address the problems of long test time and reduced test item efficiency, this paper presents a method which combines a fast correlation-based filter (FCBF) and a weighted naive Bayesian model which can identify the most effective items and make accurate quality predictions. Experimental results demonstrate that the proposed method reduces test time by around 2.59% and leads to fewer test escapes compared with the recently adopted test methods. The study shows that the proposed method can effectively reduce the test cost without jeopardizing test quality excessively.

Anchor-guided online meta adaptation for fast one-Shot instrument segmentation from robotic surgical videos.

Three-dimensional (3D) integration using through-silicon via (TSV) is an emerging technique for integrated circuit (IC) designs. A 3D IC consists of multiple dies vertically connected by TSVs. To ensure the yield of 3D ICs, each die should be tested before it is stacked, i.e., the pre-bond test. Typically, test pads are implemented in the die under test for the pre-bond test due to the limitation of current probing technologies. However, the additional test pads incur additional die area. In this paper, therefore, we propose a test cost optimization technique for the pre-bond test of 3D ICs. This technique attempts to minimize the number required power pads of each die in a wafer and the overall test time of the wafer. Simulation results show that reducing power pads can effectively reduce the number of required test pads and the wafer test time.

Error-vector-magnitude (EVM) is a system level specification that determines the overall modulation quality and exhibits strong correlation to the inherent nonidealities of a radio frequency (RF) system. In production testing, EVM tests incur significant cost due to the large number of symbols required to ensure test quality. In our approach, EVM is decomposed into its deterministic (due to static impairments: IQ mismatch, gain, AM-AM and AM-PM) and random (due to dynamic impairments: VCO phase noise, thermal noise) components. The static impairments are computed from the device under test (DUT) response to an optimized multitone test input. The dynamic impairments are computed using signal processing algorithms from the DUT test response to the same test input. The EVM of the RF system is then derived from the computed static and dynamic impairments, respectively. Experimental results show that significant reduction in test time is possible without compromising EVM test quality.

In this paper we describe an optimized BIST scheme based on reseeding of multiple polynomial Linear Feedback Shift Registers (LFSRs). The same LFSR that is used to generate pseudo-random patterns, is loaded with seeds from which it produces vectors that cover the testcubes of difficult to test faults. The scheme is compatible with scandesign and achieves full coverage as it is based on random patterns combined with a deterministic test set. A method for processing the test s et to allow for efficient encoding by the .scheme is described. Algorithms for Calculating LFSR seeds from the test set and for the selection and ordering of polynomials are described. Experimental results are provided for ISCAS-89 benchmark circuits to demonstrate the effectiveness of the scheme. The scheme allows an excellent trade-off between test data storage and test application time (number of test patterns) with a very small hardware overhead. We show the trade-off between test data storage and number of test patterns under the scheme.

This paper presents efficient built-in-self-testing (BIST) techniques for programmable capacitor arrays (PCAs) on field programmable analog array (FPAA) platforms. The proposed BIST circuits consist of switched-capacitor (SC) integrators and analog window comparators. Taking advantage of FPAA programmable resources, the proposed PCA BIST circuits can be implemented with very small hardware overhead. Also the impact of comparator threshold variations as well as other circuit parasitic effects on the efficiency of the proposed testing method is investigated. Effective circuit techniques along with new comparator designs are presented to minimize the adverse effect of comparator threshold variations. Finally, procedures for using the proposed BIST method to systematically test all PCAs on an FPAA platform are described and experimental results are presented.

Marginal hardware introduces severe reliability threats throughout the life cycle of a system. Although marginalities may not affect the functionality of a circuit immediately after manufacturing, they can degrade into hard failures and must be screened out during manufacturing test to prevent early life failures. Furthermore, their evolution in the field must be proactively monitored by periodic tests before actual failures occur. In recent years, small delay faults (SDFs) have gained increasing attention as possible indicators of marginal hardware. However, SDFs on short paths may be undetectable even with advanced timing aware ATPG. Faster-than-at-speed test (FAST) can detect such hidden delay faults (HDFs), but so far FAST has mainly been restricted to manufacturing test. This paper presents a fully autonomous built-in self-test approach for FAST, which supports in-field testing by appropriate strategies for test generation and response compaction. In particular, the required test frequencies for HDF detection are selected, such that hardware overhead and test time are minimized. Furthermore, test response compaction handles the large number of unknowns (X-values) on long paths by storing intermediate MISR-signatures in a small on-chip memory for later analysis using X-canceling transformations. A comprehensive experimental study demonstrates the effectiveness of the presented approach. In particular, the impact of the considered fault size is studied in detail.

ANSI C63.25 is a new standard that is under development by the ANSI Accredited Standards Committee C63 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> -EMC. The idea behind the ANSI C63.25 is that it will encompass all EMC test site requirements for both below 1 GHz and above 1 GHz. It is intended to be the ASC C63 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> consolidated standard for EMC test site qualification measurements. Time Domain site VSWR (TD SVSWR) is the main method used for evaluating sites above 1 GHz. Other test procedures, such as NSA measurements for test sites below 1 GHz, are well known. Therefore, this paper concentrates on introducing the TD SVSWR method. The TD SVSWR method provides an alternative method to the CISPR SVSWR method, and provides equivalent results with several added benefits, such as better defined and lower uncertainties, easier test setup and faster test time, better repeatability and abilities to provide chamber debugging information.