Built-In-Self-Testing Techniques for Programmable Capacitor Arrays

The work concerns the problem of switching processes in VLSI technology, reprogrammable analog arrays technology, and nanotechnology. Informatics is a discipline of science exploring the laws of processes of coding, processing, storing and transferring information or data. The movement and processing of Information is indissolubly connected with the switching of states of Structures carrying the data. In general, the changes of structure state can be forced through the changes of carried data parameters with unchanged structure configuration, through the switching of structure configuration or switching of the structure conformation. Switching is exhibited in different technologies by different basic elements (basic Structures or building blocks) and specified operations performed on them in order to obtain the object or product with desirable properties including also the dynamic changes of those properties. Dealing in turn with so different cases as VLSI Structures, FPAA (Field Programmable Analog Array) Structures and nanostructures, it is possible to notice, that the common feature takes a stand in solving the tasks related with them, rely on choice of certain basic elements critical for structure behavior as e.g. multicon-ductor transmission lines (MTL), configurations of FPAA substructures or whole FPAA systems, molecule conformations, and it is operated on them analyzing the internal switching processes. The design of interconnects in a high-speed integrated circuits and systems requires analysis and computer simulation based on interconnects models in the form of coupled, multiconductor transmission lines. The fundamental parameters for matrix description (or modeling, simulation and design) of MTL include the capacitance matrices. Precisely, these are the matrices per-unit of length, the capacitance coefficients matrix called Maxwell matrix of MTL and the two-terminal capacitance matrix. If the two-terminal matrix is known, the Maxwell matrix used for MTL switching characteristics estimation, can be computed from the two-terminal matrix. In the work, two methods of determination of the Maxwell matrix from measurements are presented: passive, indirect measurements and measurements with active separation. The measurements were performed basing on fabricated VLSI test structures named ST2 and AF4. The measurement results arę complemented with the accuracy analysis. Scaling of structures is conformed to fast switching, high-speed integrated YLSI/ULSI integrated circuits design. In case when the geometrical dimensions decrease, multiconductor interconnections between parts of a system become strongly coupled MTL, which in switching moments have to be recharged with smali geometry devices. In the work the method and numerical computations of scaled (in geometrical sense) MTL for its energetical characterization is presented. This can be used for proper design of MTL geometrical parameters in a YLSI/ULSI structures working with a high-speed switching. The results of measurements of the switching delay in the scaled in dimensions VLSI gates, are also included. Poor matching of the switched MTL reveals with reflections extending the time of switching and can be source of switching noises. The method of so called diagonal matching is presented in the work. The time of switching in the high-speed planar VLSI structures (driver and receiver gates connected via the long microstrip line) depends on dielectric properties of substrate under the signal and ground microstrip lines. Most important for fast switching is recharging of dielectric in the presence of the dielectric absorption phenomenon. In the work, the model of dielectric absorption and its identification algorithm based on the experimental data is presented. This model can be used for simulation of switching transients in the interconnections of different length for given technology, taking into account the dielectric absorption. Nowadays, it is apparent that many designs are evolving towards mixed-signal systems. In these kind of circuits in CMOS technology, the analog part of a system and an interface are composed frequently basing on switched capacitor (SC) technology and in the newest solution basing on field programmable analog arrays. There are two main weak points in fast switching of reconfigurable FPAA: firstly, the time of download of the configuration from supporting program or EEPROM memory with the time of transients in a FPAA chip when the download is finished and the chip undertakes its function, and secondly, for recently accessible FPAAs, there is no possibility of switching its parameters values and a part of active structure on-the-fly (during FPAA operation). In the work, the solution of fast switching of the part of working FPAA for adaptive operation is presented. The solution is based on external control of one or few CAB (Configur-able Analog Błock) in the working FPAA. The solution of the download time problem in FPAA chip operating in continuous time fashion is based on parallelization of the FPAAs and "hiding" of the download time and time of transients after download. Finally, the applications of the modified, fast switched FPAAs systems for adaptive and predictive control with possible application in the microreactors control have been presented. In the nanonetworks, an information is transferred through the state of moving molecules. In a short-distance communication (inside the closed area determined by the borders of nano-process) the state of the signaling molecules is forced through the binding via hydrogen or covalent bonds of another molecul or through the interaction of the environment's parameters.These processes in biological nanonetworks are performed in the signal transduction cascades and the same procedures are applied in the nanotechnical system of informatics. We considred these process with emphasis on the fusion of cascades. In general, these interactions lead to the switching of conformations of the molecule. In the work, we focused on biocompatible nanostructure introducing the standard, formal description of molecular structures , methodology of modeling and simulation of the conformation changes, and hierarchical description of nanonetworks useful in the switching conformation studies. The simulation methodologies based on the dynamic programming, Monte Carlo and Nascent Protein Folding algorithms are investigated. Moreover, nanotechnological, two-stage production processes based on the "gluey matrix" concept are discussed.

The use of the oscillation test strategy to test configurable analog blocks of field programmable analog arrays (FPAAs) has been proposed previously, solving the complex problem of test stimuli generation. An improvement to that technique is presented in this paper, using the resources of the FPAA to build an output response analyzer. This new approach offers a full built-in self-test scheme with no area overhead and requiring a low cost automatic test equipment. Experiments show the efficiency of the approach in detecting parametric faults of the tested components.

In this work, the effects of transient faults in Programmable Capacitor Arrays (PCA) are investigated. Usually, PCA architectures are built from a set of binary-weighted capacitor branches, which can be connected in parallel. The connection of each branch to the terminals of the capacitor array is programmed through analog switches (usually transmission gates). Transient faults, potentially caused by radiation interaction with the silicon, or by the impact of strongly ionizing particles in sensitive nodes, may temporarily close a switch in the PCA, whose default state should be open. In this case, it may occur a charge sharing process, from the equivalent capacitor (programmed into the PCA) to the temporarily connected capacitor (due to the transient effect). Therefore, after the transient, the voltage stored in the equivalent capacitor may be reduced. This effect is investigated with spice simulations. The influence of the values of the capacitors and the sizing of the analog switches (and its control logic) in the magnitude of the charge sharing effect is also investigated. Finally, some possible design-level mitigation techniques are discussed.

Functional tests of field programmable analog arrays (FPAA) are required to assess tolerance to uncontrolled and unintentional variations in the components characteristic parameters, like for example a change in the values of capacitances and gains of the differential amplifiers which may be due to aging, uncertainty (i.e., a difference between the actual and nominal values), or to an outer disturbance like radiated electromagnetic energy. The paper focuses on the latter as a cause for a possible faulty behavior: experimental results have shown that the expected performances are distorted by the presence of noise added to the useful signals due to the coupling of the external electromagnetic field with the circuitry. The results indicate that the susceptibility features depend only marginally on the specific configuration given to the FPAA, leading to the conclusion that the topology and electromagnetic characteristics of the board on which the device is mounted must be carefully designed.

We present in this paper the design and implementation aspects of the analog part of a microprocessor-based mixed-signal programmable array including a FPGA (Field Programmable Gate Array), a FPAA (Field Programmable Analog Array) and a microcontroller. Fully balanced differential amplification stages are used to provide a good immunity to the noise coming from the configurable logic blocks. Extra programmable features are introduced to compensate for layout mismatches and ensure acceptable offset and CMRR. Programmable data conversion structures with different possible combinations of resolution, number of channels and conversion speed are implemented and used for custom functions, internal monitoring and testing.

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from rapid prototyping, and forces them to expensive custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitation come from two directions: first, commercial Field Programmable Analog Arrays (FPAA) have little variability in the components offered on-chip; and second, these are only qualified for military grade temperatures, at best. However, more variability is needed for covering many sensing and control applications. Furthermore, in order to save mass, energy and wiring, there is strong interest in developing extreme environment electronics and avoiding thermal and radiation protection altogether. This means electronics that maintain correct operation while exposed to temperature extremes e.g., on Moon (-180°C to +125°C). This paper describes a recent version of a FPAA design, the JPL Self-Reconfigurable Analog Array (SRAA). It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures. A companion digital ASIC designed for algorithmic control, including a genetic algorithm implementation, is currently under fabrication.KeywordsAdaptive HardwareField Programmable Arrays

A digitally programmable and reconfigurable filter structure is presented. The design is based on a versatile continuous-time biquadratic block realized by means of digitally controllable transconductance amplifiers and programmable capacitor arrays. A specific implementation, integrated in a 3 mu m p-well CMOS process, which is capable of synthesizing a large number of even-ordered transfer functions of up to sixth order with complete control of all pole pairs and zero pairs, is discussed. The programmable filter exhibits typical pole and zero resonant frequency resolution of +or-0.25% and typical bandwidth resolution of +or-0.5% over the three-decade adjustable range from 1 kHz to 1 MHz and features typical dynamic range of 60 dB.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An analog Vector Matrix Multiplier (VMM) along with its interface through Multi-Input Translinear Elements (MITE) is compiled on a reconfigurable Field Programmable Analog Array (FPAA) on a 350nm process. The paper focuses on the tuning algorithm to set the weights on the VMM as well as to produce levels of voltage near the power supply rails, V dd , to the source-driven VMMs, by application of a wide range of input levels. The constraints during the design and implementation process, accounting for the mismatch in devices, are discussed. A significant reduction in the variation in the levels of the desired voltage has been demonstrated in the paper.

In this work, we propose an alternative for the circuital realization of analog fractional-order differentiators and integrators without using ladder networks. This alternative is obtained by a mathematical manipulation of a rational function in a similar way to the reported for the synthesis of the variable-state filters. The advantage of the proposed implementation is the requirement of only simple analog design blocks, such as integrators (of integer order), differential amplifiers and two-input adder amplifiers. Most important, contrarily to other reported solutions, the proposed realization can be fulfilled using commercially available resistors and capacitors, with a reduced number of calculations, and without negative impedance converters or inductors. In addition, the orders of the fractional derivative and integral can be modified just varying the gain of the differential amplifiers and adders. To validate the proposal of implementation, and as example of application, we present simulations (HSPICE, MATLAB) and experimental results of a first-order plus dead time plant controlled by fractional-order PI and PID controllers. The experimental results were obtained from a realization using field-programmable analog arrays. A comparison analysis highlights that the proposed alternative of implementation presents advantages regarding a Cauer-network-based realization in terms of number of active and passive elements, number of passive elements with non-commercial available values and design complexity.

In this paper, we propose a novel built-in self-test (BIST) circuit to directly measure cycle-to-cycle jitter. The clock-under-test is under-sampled by this measurement circuit and the jitter values are transformed into digital words. A time-amplified technique is applied to obtain relatively higher resolution with smaller hardware overhead. Experimental results show that our proposed circuit is able to measure the jitter providing the clock frequency up to 2 GHz with resolution of 2 picoseconds.

In this study, Izhikevich Neuron Model, which can be exhibited different behaviors, is implemented experimentally with programmable devices, FPGA (Field Programmable Gate Array) and FPAA (Field Programmable Analog Array). After testing the behaviors of neuron models through numerical analyses, the experimental setups are constructed with programmable devices. A switching mechanism, that provides convenience to observe results, is proposed as well as the advantage of FPGA's programmability. Experimental results agree with the numerical analyses results of neuron model.

This paper focuses on implementations of two modified Aihara's chaotic neuron models and a simple chaotic neural network constructed with two chaotic neurons in a programmable and reconfigurable manner with an analog programmable device, FPAA (Field Programmable Analog Array). After testing the chaotic behaviors of two chaotic neuron models and a simple chaotic neural network through numerical analyses that consist of time domain responses, phase portrait illustrations and bifurcation diagrams, the experimental setup is constructed with a FPAA device. The parametric adjustments of chaotic neural structures are possible with the proposed flexible design methodology and different chaotic neuron models are constructed on the same reconfigurable device without any hardware changes. Experimental results verify the dynamic behaviors of these chaotic neural structures and demonstrate the efficiency of programmable implementations.

A low power second order hybrid loopfilter Sigma-Delta modulator with high resolution is presented. The structure is composed by a first active integrator followed by a switched-capacitor (SC) integrator. This modulator architecture exploits the coefficient scaling property of the active integrator, while the SC integrator is modified to shift its pole from inside the unit circle to z=1 at DC in the z-domain. Poles of the loopfilter are zeroes of the noise transfer function (NTF). As a result the NTF zero is also shifted to z=1. This NTF zero compensation for the SC integrator will result in better in-band noise suppression & improved noise shaping. The second order hybrid sigma-delta modulator with a 4-bit quantizer and an oversampling ratio (OSR) of 32 is simulated in simulink. The modulator can achieve 89dB SNDR with a dynamic range of 91dB.

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

In this paper, we present TAO-BIST, a framework for testing register-transfer level (RTL) controller-datapath circuits using built-in self-test (BIST). Conventional BIST techniques at the RTL generally introduce more testability hardware than is necessary, thereby causing unnecessary area, delay and power overheads. They have typically been applied to only application-specific integrated circuits (ASICs). TAO-BIST adopts a three-phased approach to provide an efficient BIST framework at the RTL. In the first phase, we identify and add an initial set of test enhancements to the given circuit. In the second phase, we use regular-expression based high-level symbolic testability analysis of a BIST model of the circuit to completely encapsulate justification/propagation information for the modules under test. The regular expressions so obtained are then used to construct a Boolean function in the final phase for determining a test enhancement solution that meets delay constraints with minimal area overheads. Our method is applicable to a wide spectrum of circuits including ASICs, application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs) and microprocessors. Experimental results on a number of benchmark circuits show that high fault coverage (>99%) can be obtained with our scheme. The average area and delay overheads due to TAO-BIST are only 6.0%, and 1.5%, respectively. The test application time to achieve the high fault coverage for the whole controller-datapath circuit is also quite low.