Programmable analog hardware: a case study

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from rapid prototyping, and forces them to expensive custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitation come from two directions: first, commercial Field Programmable Analog Arrays (FPAA) have little variability in the components offered on-chip; and second, these are only qualified for military grade temperatures, at best. However, more variability is needed for covering many sensing and control applications. Furthermore, in order to save mass, energy and wiring, there is strong interest in developing extreme environment electronics and avoiding thermal and radiation protection altogether. This means electronics that maintain correct operation while exposed to temperature extremes e.g., on Moon (-180°C to +125°C). This paper describes a recent version of a FPAA design, the JPL Self-Reconfigurable Analog Array (SRAA). It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures. A companion digital ASIC designed for algorithmic control, including a genetic algorithm implementation, is currently under fabrication.KeywordsAdaptive HardwareField Programmable Arrays

Quantum-dot cellular automata (QCA) is a promising, emerging nano-technology based on single electron effects in quantum dots and molecules. This paper presents design, implementation and simulation of a configurable logic block for a field programmable gate arrays (FPGA) by QCA. Previous works focus on QCA-based FPGA that have fixed logic and programmable interconnection or programmable logic and fixed interconnection; however, proposed structures in this paper have programmable logic and programmable interconnection. The presented look-up table implemented with novel structure which has been allowed as frequently as the read/write operation occurs, also acts as a pipeline. In this paper, we presented novel decoders and multiplexers and implemented with QCA, designed with the minimum number of majority gates and cells. Finally, a new configurable logic block (CLB) is designed, implemented and simulated in the QCA, which used signal distribution network method to avoid the coplanar problem of crossing wires. Also, QCADesigner software is used for detailed layout and QCADesigner attend with HDLQ verilog are used for circuit simulation. The proposed CLB is simulated with programming by the QCADesigner software. The area and delay of QCA-based CLB presented in this paper compared to the CLB based on CMOS, nanomaterial and CNT (32 nm). Results show that proposed CLB will do the task with a minimum clock and can be configured as a FPGA.

This paper presents the design and simulation of a circuit consisting of multiple interacting configurable logic blocks (CLBs) using quantum-dot cellular automata (QCA). Previous work on QCA-based field-programmable gate arrays (FPGAs) has focused on fixed logic and programmable interconnect. In contrast, this work uses CLBs consisting of look-up tables (LUTs). These CLBs have been previously presented in isolation. This paper presents two main contributions. First, we improve the latency and area of the existing CLBs. Second, we simulate four connected CLBs acting as a very simple FPGA. We configure this FPGA to emulate a ripple-carry adder and analyze latency and throughput. We employ a multilevel approach to design specification and simulation. QCADesigner software is used for detailed layout and simulation of the individual CLB. For simulations of multiple-CLB circuits, we use the high-level HDLQ Verilog library instead. This hybrid approach provides a high degree of confidence in reasonable simulation time.

This paper presents an I/sub DDQ/-based test strategy for detecting bridging faults in the logic resources of reprogrammable field programmable gate arrays (FPGAs). The proposed approach utilizes the programmability of the configurable logic blocks (CLBs) to achieve 100 percent coverage of I/sub DDQ/ testable bridging faults. We use a hierarchical approach for generating tests and configurations. At the chip level, the CLBs are viewed as a homogeneous two-dimensional array. Two configuration strategies are suggested to simultaneously test each CLB. Within each CLB, we test for external bridging faults between the combinational and sequential logic modules (e.g., flip-flops, multiplexers, lookup tables), Finally, we test for internal bridging faults within each module based on their implementation. Since reconfiguration programming time dominates total test time, even with slow I/sub DDQ/ vectors, we use a bottom-up test generation approach to minimize the number of programming phases first and, then, to minimize the number of test vectors. The Xilinx XC4000 family of SRAM-based FPGAs is used as an example application of the proposed approach. One hundred percent coverage for I/sub DDQ/-testable bridging faults is achieved in five programming phases and 16 I/sub DDQ/ vectors. Since the lookup tables in the CLB can be configured as RAM, the RAM modes are also tested. This requires a further phase, using 48 test vectors and 38 I/sub DDQ/ measurements.

Field Programmable Gate Array Reliability Analysis Using the Dynamic Flowgraph Methodology

With the development of digital integrate circuit system which is based on Field Programmable Gate Arrays (FPGA), the request on FPGA test technique is becoming higher and higher. The Boundary Scan Technique and Built-In Self-Test (BIST) technique appear in succession, however, these techniques dont implement Configurable Logic Block (CLB) fault diagnose and fault orientation. Arrays-based technique was advanced, which also have some problems about masking of faults and too many reconfiguration times. According to these problems, A Novel Shift Register-based technique for Fault Orientation of FPGA Configurable Logic Blocks was advanced. The paper analyses the design theory about core circuit configure, and has important significance impact on Fault Orientation of FPGA Configurable Logic Blocks.

The increasing popularity of the field programmable gate array (FPGA) has generated a great deal of interest for FPGA design problems. Due to the fact that FPGAs are mainly characterized both by high integration rate and reprogrammability, they are useful for complex image processing. However, fast processing is not possible without parallel processing; also traditional integration methods are not sufficient enough. Thus, one possible way is to adapt the processing algorithm to the FPGA architecture and to avoid general methods of schematic description, allowing an easily implantation, but not an optimum partitioning-routing. With this aim, we tried to minimize the number of CLBs (configurable logic block) in the FPGA, to logical functions (addition, multiplication, comparison etc.) dedicated to segmentation, classification, as well as filtering operations. This is done by expressing the whole architecture-function to integrate as Boolean constraints.

The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA's configurable logic blocks (CLBs). The defects affecting the FPGA's interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources (king-shifting and horse-allocation) are introduced and compared.

A Field Programmable Gate Array (FPGA) consists of an array of identical configurable logic blocks (CLBs), each capable of implementing any boolean function with a bounded number of inputs. Such architectural regularity provides an inherent redundancy which can be exploited for fault tolerance and yield enhancement. In this paper we examine the problem of reconfiguring the placement of a circuit on an FPGA to tolerate a given fault pattern in the array of CLBs. The primary objective of the placement reconfiguration is to minimize timing degradation. The secondary objective is to minimize the amount of re-programming (both in the CLBs and in the routing switches) in the reconfiguration process. The concept of a slack neighborhood graph is introduced as a general tool for timing driven reconfiguration with a bounded increase in critical path delay. Our algorithm simultaneously achieves both provably low timing degradation and low reprogramming cost. Slack neighborhood graphs are of independent interest due to their possible applications to the timing driven placement problem. For a wide range of fault probabilities and circuits our algorithm successfully reconfigures the placement with less than 1% degradation in the circuit delay.

The increased circuit complexity of field programmable gate array (FPGA) poses a major challenge in the testing of FPGAs. One of the test challenges is to detect the delay faults in high‐speed circuits. Built‐in‐self‐test (BIST) Technique is an ease solution compared with expensive automatic test equipment. In this work, a BIST structure is proposed to detect the delay faults in the various resources of the FPGA such as multiplier, digital signal processing (DSP) block, look‐up tables etc. and interconnects of FPGA. The authors have also proposed a full‐diagnosable BISTer structure that improves the testing efficiency of the logic BIST. The proposed BISTer structure can diagnose the faulty configurable logic block (CLB), when all the CLBs in the 2 × 3 BIST are faulty. The proposed scheme has been simulated in Xilinx Vertex FPGA, using ISE tool, Jbits3.0 API and XHWI (Xilinx HardWare Interface) and MATLAB7.0. The result shows significant improvement compared with earlier BIST methods.

This paper presents efficient built-in-self-testing (BIST) techniques for programmable capacitor arrays (PCAs) on field programmable analog array (FPAA) platforms. The proposed BIST circuits consist of switched-capacitor (SC) integrators and analog window comparators. Taking advantage of FPAA programmable resources, the proposed PCA BIST circuits can be implemented with very small hardware overhead. Also the impact of comparator threshold variations as well as other circuit parasitic effects on the efficiency of the proposed testing method is investigated. Effective circuit techniques along with new comparator designs are presented to minimize the adverse effect of comparator threshold variations. Finally, procedures for using the proposed BIST method to systematically test all PCAs on an FPAA platform are described and experimental results are presented.

Field Programmable Gate Arrays (FPGAs) are an increasingly popular choice of platform for the implementation of cryptographic systems. Until recently, designers using FPGAs had less than optimal choices for a source of truly random bits. In this paper we extend a technique that uses on-chip jitter and PLLs to a much larger class of FPGAs that do not contain PLLs. Our design uses only the Configurable Logic Blocks (CLBs) common to all FPGAs, and has a self-testing capability. Using the intrinsic jitter contained in digital circuits, we produce random bits at speeds of up to 0.5 Mbits/second with good statistical characteristics. We discuss the engineering challenges of extracting random bits from digital circuits, and we report the results of running standard statistical tests (NIST) on the output generated by our system.

Over the last decade, field programmable gate arrays (FPGAs) have embraced heterogeneity in a transformative way by leveraging emerging memory devices along with conventional CMOS-based devices to realize technology-specific benefits. Memristive device technologies exhibit desirable characteristics such as non-volatility, scalability, near-zero leakage, radiation hardness, and more, making them promising alternatives for SRAM cells found in conventional SRAM-based FPGAs. In recent years, a significant amount of research has been performed to take advantage of these emerging technologies to develop fundamental building blocks of FPGAs like hybrid CMOS-memristive look-up tables (LUTs) and configurable logic blocks (CLBs). In this chapter, we will provide a brief overview of the previous work on hybrid CMOS-memristive FPGAs and their corresponding opportunities and challenges.

In recent years, Spiking Neural Networks (SNNs) have been increasingly deployed on Field Programmable Gate Arrays (FPGAs) for enabling low-energy AI inference. SNNs aim to enable more biomimetic processing than ANNs, thereby enabling more event-driven computing along with using cheaper arithmetic than multiply and accumulate operations. However, deploying large SNNs to achieve acceptable accuracy requires extensive use of configurable logic blocks (CLBs), leading to additional programmable routing and critical path delay. This study addresses these issues by exploring soft-logic architectures to reduce resource utilization for SNNs. We propose two architectures that provide a more efficient mapping of logic primitives for SNNs, reducing CLB usage by 13.49% and 20.13% compared to the Intel Stratix10 baseline. Implemented with an advanced technology node, these architectures achieve an average reduction of 8.30% and 7.30% in CLB area and reduce critical path delay by 2.72% and 3.42%, respectively, enabling larger SNNs with faster inference within the same programmable fabric.