Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

The work concerns the problem of switching processes in VLSI technology, reprogrammable analog arrays technology, and nanotechnology. Informatics is a discipline of science exploring the laws of processes of coding, processing, storing and transferring information or data. The movement and processing of Information is indissolubly connected with the switching of states of Structures carrying the data. In general, the changes of structure state can be forced through the changes of carried data parameters with unchanged structure configuration, through the switching of structure configuration or switching of the structure conformation. Switching is exhibited in different technologies by different basic elements (basic Structures or building blocks) and specified operations performed on them in order to obtain the object or product with desirable properties including also the dynamic changes of those properties. Dealing in turn with so different cases as VLSI Structures, FPAA (Field Programmable Analog Array) Structures and nanostructures, it is possible to notice, that the common feature takes a stand in solving the tasks related with them, rely on choice of certain basic elements critical for structure behavior as e.g. multicon-ductor transmission lines (MTL), configurations of FPAA substructures or whole FPAA systems, molecule conformations, and it is operated on them analyzing the internal switching processes. The design of interconnects in a high-speed integrated circuits and systems requires analysis and computer simulation based on interconnects models in the form of coupled, multiconductor transmission lines. The fundamental parameters for matrix description (or modeling, simulation and design) of MTL include the capacitance matrices. Precisely, these are the matrices per-unit of length, the capacitance coefficients matrix called Maxwell matrix of MTL and the two-terminal capacitance matrix. If the two-terminal matrix is known, the Maxwell matrix used for MTL switching characteristics estimation, can be computed from the two-terminal matrix. In the work, two methods of determination of the Maxwell matrix from measurements are presented: passive, indirect measurements and measurements with active separation. The measurements were performed basing on fabricated VLSI test structures named ST2 and AF4. The measurement results arę complemented with the accuracy analysis. Scaling of structures is conformed to fast switching, high-speed integrated YLSI/ULSI integrated circuits design. In case when the geometrical dimensions decrease, multiconductor interconnections between parts of a system become strongly coupled MTL, which in switching moments have to be recharged with smali geometry devices. In the work the method and numerical computations of scaled (in geometrical sense) MTL for its energetical characterization is presented. This can be used for proper design of MTL geometrical parameters in a YLSI/ULSI structures working with a high-speed switching. The results of measurements of the switching delay in the scaled in dimensions VLSI gates, are also included. Poor matching of the switched MTL reveals with reflections extending the time of switching and can be source of switching noises. The method of so called diagonal matching is presented in the work. The time of switching in the high-speed planar VLSI structures (driver and receiver gates connected via the long microstrip line) depends on dielectric properties of substrate under the signal and ground microstrip lines. Most important for fast switching is recharging of dielectric in the presence of the dielectric absorption phenomenon. In the work, the model of dielectric absorption and its identification algorithm based on the experimental data is presented. This model can be used for simulation of switching transients in the interconnections of different length for given technology, taking into account the dielectric absorption. Nowadays, it is apparent that many designs are evolving towards mixed-signal systems. In these kind of circuits in CMOS technology, the analog part of a system and an interface are composed frequently basing on switched capacitor (SC) technology and in the newest solution basing on field programmable analog arrays. There are two main weak points in fast switching of reconfigurable FPAA: firstly, the time of download of the configuration from supporting program or EEPROM memory with the time of transients in a FPAA chip when the download is finished and the chip undertakes its function, and secondly, for recently accessible FPAAs, there is no possibility of switching its parameters values and a part of active structure on-the-fly (during FPAA operation). In the work, the solution of fast switching of the part of working FPAA for adaptive operation is presented. The solution is based on external control of one or few CAB (Configur-able Analog Błock) in the working FPAA. The solution of the download time problem in FPAA chip operating in continuous time fashion is based on parallelization of the FPAAs and "hiding" of the download time and time of transients after download. Finally, the applications of the modified, fast switched FPAAs systems for adaptive and predictive control with possible application in the microreactors control have been presented. In the nanonetworks, an information is transferred through the state of moving molecules. In a short-distance communication (inside the closed area determined by the borders of nano-process) the state of the signaling molecules is forced through the binding via hydrogen or covalent bonds of another molecul or through the interaction of the environment's parameters.These processes in biological nanonetworks are performed in the signal transduction cascades and the same procedures are applied in the nanotechnical system of informatics. We considred these process with emphasis on the fusion of cascades. In general, these interactions lead to the switching of conformations of the molecule. In the work, we focused on biocompatible nanostructure introducing the standard, formal description of molecular structures , methodology of modeling and simulation of the conformation changes, and hierarchical description of nanonetworks useful in the switching conformation studies. The simulation methodologies based on the dynamic programming, Monte Carlo and Nascent Protein Folding algorithms are investigated. Moreover, nanotechnological, two-stage production processes based on the "gluey matrix" concept are discussed.

This paper discusses the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in open-source SciLab / Xcos based toolset. Analog computation becomes relevant with the advent of FPAA devices, particularly the SoC FPAA devices and resulting design tools. Analog and digital systems have tools to model resolution and computational noise and computation energy; analog and digital approaches have their own optimal computing regions. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches. These discussions begin the framework for a theory of analog algorithm complexity theory, and careful methods for comparison of techniques.

A Field Programmable Analog Array (FPAA) is presented based on switched capacitor technology. The architecture offers an unconstrained topology similar to its digital counterpart, containing an array of identical undedicated analog cells. This makes it possible to program both the functionality of each cell and the interconnect between cells. As a result a large number of diverse architectures may be implemented. The analog array can be programmed to perform many of the routine tasks associated with control systems design. Its linear and non-linear signal processing abilities can provide a wide range of waveform generation functions. The device can also be programmed for precise phase and magnitude characteristics. Some examples related to control systems are discussed.

This paper presents a novel architecture for mixed-signal SoC, which integrates a Field Programmable Analog Array (FPAA) into a SoC based on 32-bit RISC CPU. The FPAA unit can be configured as Filter, Comparator, Gain Amplifier, and so on. The proposed mixed-signal SoC can transform the intermediate frequency (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing, besides this, which can transmit the modulated IF signals which are converted from baseband signals by digital up-conversion (DUC). The proposed mixed-signal SoC is a transceiver on chip actually, due to the internal integrated IPs, such as ADC, DAC, DDC and DUC, which can provide smaller board area, lower power consumption and the system cost for the product development of transceiver. This design will have a good potential for wireless communication applications.

The drive towards shorter design cycles for analog integrated circuits has given impetus to several developments in the area of Field-Programmable Analog Arrays (FPAAs). Various approaches have been taken in implementing structural and parametric programmability of analog circuits. Recent extensions of this work have married FPAAs to their digital counterparts (FPGAs) along with data conversion interfaces, to form Field-Programmable Mixed-Signal Arrays (FPMAs). This survey paper reviews work to date in the area of programmable analog and mixed-signal circuits. The body of work reviewed includes university and industrial research, commercial products and patents. A time-line of important achievements in the area is drawn, the status of various activities is summarized, and some directions for future research are suggested.

We present a mixed-signal system for extracting hemodynamic parameters in real-time from noisy electrical bioimpedance (EBI) measurements in an energy-efficient manner. The proof-of-concept system consists of floating-gate-based analog signal processing (ASP) electronics implemented on a field programmable analog array (FPAA) chip interfaced with an on-chip low-power microcontroller. Physiological features important for calculating hemodynamic parameters (e.g., heart rate, blood volume, and blood flow) are extracted using the custom signal processing circuitry, which consumes a total power of 209 nW. Testing of the signal processing circuitry has been performed using ~580 sec of an impedance plethysmography dataset collected from the knee of a subject using a custom analog EBI front-end. Results show the similarities of variations in heart rate, blood volume, and blood flow calculated using features extracted by the ASP circuitry implemented on an FPAA and a MATLAB digital signal processing algorithm.

Field Programmable Gate Arrays (FPGAs) and Field Programmable Analog Arrays (FPAAs) are devices used in applications where real time is considered the main feature. In this paper some important new trends in the field of analog devices are presented. Starting with a short presentation of the technology followed by a few examples of implemented applications, the paper ends up with two new ideas, mixed signal architecture and evolvable hardware. In summary, this new field of FPAA reprogrammable devices appears as a new challenge when dealing with real-time control.

The Coordinate Rotation Digital Computer (CORDIC) algorithm has emerged as a pivotal method for executing trigonometric and various mathematical operations within digital systems. Field-Programmable Gate Arrays (FPGAs) have witnessed a remarkable surge in adoption for implementing the CORDIC algorithm owing to their inherent flexibility and exceptional performance capabilities. This paper endeavours to provide a comprehensive overview of FPGA implementations of the CORDIC algorithm, elucidating both the advantages and challenges associated with this methodology. It thoroughly examines various FPGA architectures customized for CORDIC implementation, meticulously analyzing their respective trade-offs regarding resource utilization, performance metrics, and accuracy levels. Moreover, the paper explores numerous applications where the FPGA-based CORDIC algorithm shines, illustrating its adaptability across diverse domains like digital signal processing and control systems. These applications underscore the algorithm's efficacy in addressing real-world challenges and its potential to significantly augment system performance and efficiency.By furnishing profound insights into FPGA-based CORDIC implementations, this paper serves as an invaluable resource for engineers and researchers keen on harnessing the capabilities of FPGAs for high-performance mathematical computations in digital systems.

Present-day numerical relays provide remarkable capabilities such as monitoring, recording and communication. These capabilities are considered as secondary priority whereas speed and reliability are the two most important characteristics of a protective relay. Even though present-day numerical relays have provided considerable capabilities and advantages, they have not improved speed of operation in comparison to their solid-state counterparts. The idea of applying mixed signals processing using advanced analogue and digital technology in several applications has started. Use of advanced programmable analogue technology, which is known as field programmable analogue arrays (FPAAs), seems to have the potential to be used in protective relays. Hybrid hardware using both digital signal processor (DSP) and FPAAs is proposed to implement mho distance relay considering capacitor voltage transformer (CVT) transient supervision for low and high system impedance ratio (SIR) systems. Test results are reported and compared with a commercial relay test results.

Analog signal processing (ASP) can be used to decrease energy consumption by several orders of magnitude over completely digital applications. Low-power field programmable analog arrays (FPAA) have been previously used by analog designers to decrease energy consumption. Combining ASP with an FPAA, energy consumption of these systems can be further reduced. For ASP to be most functional, it must achieve rail-to-rail operation to maintain a high dynamic range. This work strives to further reduce power consumption in reconfigurable analog circuitry by presenting a novel data converter that utilizes ASP and rail-to-rail operation. Rail-to-Rail operation is achieved in the data converter with the use of an operational amplifier presented in this work. This efficient yet elementary data converter has been fabricated in a 0.5$\mu$m standard CMOS process. Additionally, this work looks deeper into the challenges of students working remotely, how MATLAB can be used to create circuit design tools, and how these developmental tools can be used by circuit design students.

In this study, Izhikevich Neuron Model, which can be exhibited different behaviors, is implemented experimentally with programmable devices, FPGA (Field Programmable Gate Array) and FPAA (Field Programmable Analog Array). After testing the behaviors of neuron models through numerical analyses, the experimental setups are constructed with programmable devices. A switching mechanism, that provides convenience to observe results, is proposed as well as the advantage of FPGA's programmability. Experimental results agree with the numerical analyses results of neuron model.

Great achievements in the area of evolvable hardware have been reported in the last decade. Evolvable hardware comprises an evolutionary algorithm, such as a genetic algorithm, and a reconfigurable hardware, such as field programmable analog arrays and field programmable gate arrays. In these devices, internal circuits' connections can be programmed for specific applications. In this paper, configurability and evolvability issues are addressed in the domain of synthesis of analog circuits on an analog reconfigurable platform. First, implementation aspects and characteristics are presented: then some circuits' syntheses are discussed. Finally the authors present their view on how the techniques and approaches studied in the domain of the synthesis of analog circuits could be extended and applied in other domains, such as molecular electronics.

We present in this paper the design and implementation aspects of the analog part of a microprocessor-based mixed-signal programmable array including a FPGA (Field Programmable Gate Array), a FPAA (Field Programmable Analog Array) and a microcontroller. Fully balanced differential amplification stages are used to provide a good immunity to the noise coming from the configurable logic blocks. Extra programmable features are introduced to compensate for layout mismatches and ensure acceptable offset and CMRR. Programmable data conversion structures with different possible combinations of resolution, number of channels and conversion speed are implemented and used for custom functions, internal monitoring and testing.

The insertion of communication networks in closed-loop of digital control systems makes the system synthesis and analysis complex. In this paper, we consider the combination of classical reliability, risk and safety evaluation with typical control system through digital networked control systems. The main purpose is to study the influence of transmission delays and packet dropouts on the reliability of digital networked control systems by using a modified statistical method-Monte Carlo simulation. The behaviors of two types of fault are modelled by different statistical distribution. The control strategies we apply for digital control systems are Proportion Integration Differentiation control strategies, generated by Genetic Algorithm. In terms of a realistic system model, we evaluate and compare the influences on the reliability of digital networked control systems with different control strategies from quantitative aspect. Numerical examples are presented to illustrate the effectiveness and correctness of the approach.

A digital wide-band system for damping ring instabilities in an accelerator is presented. With increased beam intensity, the losses of an accumulator ring tend to increase due to the onset of various instabilities in the beam. An analog feedback damper system has been implemented at Los Alamos National Laboratory. This analog system, while functional, has certain limitations and a lack of programmability, which can be overcome by a digital solution. A digital feedback damper system is being designed through a collaborative effort by researchers at Oakridge National Laboratory, Los Alamos National Laboratory, and the University of Wisconsin. This system, which includes analog-to-digital converters, field programmable gate arrays and digital-to-analog converters can equalize errors inherent to analog systems, such as dispersion due to amplifiers/cables, gain mismatches, and timing adjustments. The digital system features programmable gains and delays, and programmable equalizers that are implemented using digital FIR and comb filters. The flexibility of the digital system allows it to be customized to implement different configurations and extended to address other diagnostic problems.