A field programmable analog array and its application

The work concerns the problem of switching processes in VLSI technology, reprogrammable analog arrays technology, and nanotechnology. Informatics is a discipline of science exploring the laws of processes of coding, processing, storing and transferring information or data. The movement and processing of Information is indissolubly connected with the switching of states of Structures carrying the data. In general, the changes of structure state can be forced through the changes of carried data parameters with unchanged structure configuration, through the switching of structure configuration or switching of the structure conformation. Switching is exhibited in different technologies by different basic elements (basic Structures or building blocks) and specified operations performed on them in order to obtain the object or product with desirable properties including also the dynamic changes of those properties. Dealing in turn with so different cases as VLSI Structures, FPAA (Field Programmable Analog Array) Structures and nanostructures, it is possible to notice, that the common feature takes a stand in solving the tasks related with them, rely on choice of certain basic elements critical for structure behavior as e.g. multicon-ductor transmission lines (MTL), configurations of FPAA substructures or whole FPAA systems, molecule conformations, and it is operated on them analyzing the internal switching processes. The design of interconnects in a high-speed integrated circuits and systems requires analysis and computer simulation based on interconnects models in the form of coupled, multiconductor transmission lines. The fundamental parameters for matrix description (or modeling, simulation and design) of MTL include the capacitance matrices. Precisely, these are the matrices per-unit of length, the capacitance coefficients matrix called Maxwell matrix of MTL and the two-terminal capacitance matrix. If the two-terminal matrix is known, the Maxwell matrix used for MTL switching characteristics estimation, can be computed from the two-terminal matrix. In the work, two methods of determination of the Maxwell matrix from measurements are presented: passive, indirect measurements and measurements with active separation. The measurements were performed basing on fabricated VLSI test structures named ST2 and AF4. The measurement results arę complemented with the accuracy analysis. Scaling of structures is conformed to fast switching, high-speed integrated YLSI/ULSI integrated circuits design. In case when the geometrical dimensions decrease, multiconductor interconnections between parts of a system become strongly coupled MTL, which in switching moments have to be recharged with smali geometry devices. In the work the method and numerical computations of scaled (in geometrical sense) MTL for its energetical characterization is presented. This can be used for proper design of MTL geometrical parameters in a YLSI/ULSI structures working with a high-speed switching. The results of measurements of the switching delay in the scaled in dimensions VLSI gates, are also included. Poor matching of the switched MTL reveals with reflections extending the time of switching and can be source of switching noises. The method of so called diagonal matching is presented in the work. The time of switching in the high-speed planar VLSI structures (driver and receiver gates connected via the long microstrip line) depends on dielectric properties of substrate under the signal and ground microstrip lines. Most important for fast switching is recharging of dielectric in the presence of the dielectric absorption phenomenon. In the work, the model of dielectric absorption and its identification algorithm based on the experimental data is presented. This model can be used for simulation of switching transients in the interconnections of different length for given technology, taking into account the dielectric absorption. Nowadays, it is apparent that many designs are evolving towards mixed-signal systems. In these kind of circuits in CMOS technology, the analog part of a system and an interface are composed frequently basing on switched capacitor (SC) technology and in the newest solution basing on field programmable analog arrays. There are two main weak points in fast switching of reconfigurable FPAA: firstly, the time of download of the configuration from supporting program or EEPROM memory with the time of transients in a FPAA chip when the download is finished and the chip undertakes its function, and secondly, for recently accessible FPAAs, there is no possibility of switching its parameters values and a part of active structure on-the-fly (during FPAA operation). In the work, the solution of fast switching of the part of working FPAA for adaptive operation is presented. The solution is based on external control of one or few CAB (Configur-able Analog Błock) in the working FPAA. The solution of the download time problem in FPAA chip operating in continuous time fashion is based on parallelization of the FPAAs and "hiding" of the download time and time of transients after download. Finally, the applications of the modified, fast switched FPAAs systems for adaptive and predictive control with possible application in the microreactors control have been presented. In the nanonetworks, an information is transferred through the state of moving molecules. In a short-distance communication (inside the closed area determined by the borders of nano-process) the state of the signaling molecules is forced through the binding via hydrogen or covalent bonds of another molecul or through the interaction of the environment's parameters.These processes in biological nanonetworks are performed in the signal transduction cascades and the same procedures are applied in the nanotechnical system of informatics. We considred these process with emphasis on the fusion of cascades. In general, these interactions lead to the switching of conformations of the molecule. In the work, we focused on biocompatible nanostructure introducing the standard, formal description of molecular structures , methodology of modeling and simulation of the conformation changes, and hierarchical description of nanonetworks useful in the switching conformation studies. The simulation methodologies based on the dynamic programming, Monte Carlo and Nascent Protein Folding algorithms are investigated. Moreover, nanotechnological, two-stage production processes based on the "gluey matrix" concept are discussed.

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.

A field programmable analogue array (FPAA) for biomedical applications is introduced in this paper. The proposed FPAA is based on operational transconductance amplifier (OTA). The FPAA consists of configurable analogue blocks (CABs) arranged in three sections. Each section implements an OTA-C filter of reconfigurable order with variable gain, and bandwidth. Direct connections between CABs within a section, and between sections are present. The proposed reconfigurable FPAA permits different connections between its sections, providing a wide range of possible applications. Allowing the implementation of full biomedical systems, such as the analogue front-end (AFE) for biopotential signal acquisition. Reconfigurability and functionality of the proposed FPAA architecture is demonstrated through mapping of low power filters and AFE on FPAA. Simulations results for a 90 nm CMOS technology are given. The simulation results of filter and AFE on FPAA are compared to off- FPAA simulations.

By using the Field Programmable Analog Array (FPAA) IC with embedded switched capacitor techniques, the circuit design for a neuron is proposed. First, the FPAA IC and EDA software platform are introduced. Second, the architecture and working principle of the FPAA neuron circuit are present. Third, by using the FPAA EDA software and hardware developing platform, the FPAA neuron circuit has been designed and tested.

This paper discusses the first step in analog (and mixed signal) abstraction utilized in large-scale Field Programmable Analog Arrays (FPAA), encoded in open-source SciLab / Xcos based toolset. Analog computation becomes relevant with the advent of FPAA devices, particularly the SoC FPAA devices and resulting design tools. Analog and digital systems have tools to model resolution and computational noise and computation energy; analog and digital approaches have their own optimal computing regions. Abstraction of Blocks in the FPAA block library makes the SoC FPAA ecosystem accessible to system-level designers while still enabling circuit designers the freedom to build at a low level. The FPAA block library provides a starting point for discussing the fundamental block concepts of analog computational approaches. These discussions begin the framework for a theory of analog algorithm complexity theory, and careful methods for comparison of techniques.

ABSTRACTA novel fully differential digitally programmable current conveyor (DPCCII) is presented in this paper. The programmability of the proposed DPCCII is achieved using three‐bit MOS R‐2R ladder current division network. The DPCCII is used to realize a field programmable analog array (FPAA). The FPAA consists of seven configurable analog blocks arranged in a hexagonal form. The FPAA power consumption is 72.3 mW from 1 V voltage supply. A second‐order programmable universal filter is realized using the proposed FPAA as an application. All the circuits are realized and simulated using 90 nm IBM CMOS technology model under balanced supply voltage of ±0.5 V. Copyright © 2012 John Wiley & Sons, Ltd.

The drive towards shorter design cycles for analog integrated circuits has given impetus to several developments in the area of Field-Programmable Analog Arrays (FPAAs). Various approaches have been taken in implementing structural and parametric programmability of analog circuits. Recent extensions of this work have married FPAAs to their digital counterparts (FPGAs) along with data conversion interfaces, to form Field-Programmable Mixed-Signal Arrays (FPMAs). This survey paper reviews work to date in the area of programmable analog and mixed-signal circuits. The body of work reviewed includes university and industrial research, commercial products and patents. A time-line of important achievements in the area is drawn, the status of various activities is summarized, and some directions for future research are suggested.

Feedback control for the active noise cancellation can be done with analog or digital circuitry. Although digital approach is steadily gaining ground, analog control still has its uses. Short control latency is the feature of an analog controller—it has the shortest possible delay. Its drawback is the limited flexibility for adjustable or adaptive solutions. To overcome this, digitally adjustable analog controllers can be used. A potential implementation for such controller uses field programmable analog array (FPAA) technology. With FPAAs both the filter parameters and structure are digitally adjustable, even during the operation. A development environment around the FPAA controller has been devised. It consists of the measurement system, an optimizer that calculates the optimum controller response, programming software, and actual FPAA hardware with its embedded software. The complete system is packaged tightly to a compact form. It can be used for evaluation purposes in acoustics laboratory conditions. Such a system has been evaluated in active noise insulation application. It has proven to operate as simulated and optimized also in real-world tests. The future development of the system includes further miniaturization, controller networking, and possible integration inside the sound insulation system.

This paper presents a novel architecture for mixed-signal SoC, which integrates a Field Programmable Analog Array (FPAA) into a SoC based on 32-bit RISC CPU. The FPAA unit can be configured as Filter, Comparator, Gain Amplifier, and so on. The proposed mixed-signal SoC can transform the intermediate frequency (IF) analog signal to baseband digital signal and realize the real-time baseband signal processing, besides this, which can transmit the modulated IF signals which are converted from baseband signals by digital up-conversion (DUC). The proposed mixed-signal SoC is a transceiver on chip actually, due to the internal integrated IPs, such as ADC, DAC, DDC and DUC, which can provide smaller board area, lower power consumption and the system cost for the product development of transceiver. This design will have a good potential for wireless communication applications.

In this paper, the prototyping of 3rd order, 4th order, 5th order, and 6th order sigma-delta analog to digital converters (Σ∆ ADCs) has been presented. It summarily portrays the method implemented for configuration and reconfiguration of the proposed circuits by using Field Programmable Analog Array (FPAA). Their function was determined in the time domain at a constant 1 V supply voltages which is a sinewave input signal of 20 kHz frequency. The sampling frequency is fs = 4 MHz and the Oversampling ratio is OSR = 50 which yields a bandwidth of 40 kHz. Practical experimentation of the circuits was carried out using the AN221E04 FPAA device from Anadigm. Circuit realization of 3rd order, 4th order, 5th order, and 6th order sigma-delta analog to digital converters (Σ∆ ADCs) using FPAA are shown in figures. Also, sinusoidal input and output waveforms of implemented architectures are shown. A comparison of the proposed designed circuits with the various sigma-delta modulators published in the previous paper is also shown. The proposed sigma-delta modulators can be applied in the investigation and practical study of designing programmable analog devices and systems based on FPAA.

This paper presents a solid foundation for implementing analog vector-matrix multipliers (VMMs) in field-programmable analog arrays (FPAAs). Custom analog VMMs have been demonstrated to be 1000 times more power efficient than commercial digital implementations. However, no previous analog VMM discussion has carefully provided all of the implementation and performance considerations needed to utilize such a system. We utilize the FPAA because it provides an ideal platform for embedding low-power analog processing into larger systems. FPAAs allow the analog processing system to be rapidly prototyped, implemented at low cost, and easily reconfigured in the field. This paper can double as a complete analog VMM design specification, as well as a systematic tutorial on developing general systems with FPAA hardware. We detail the aspects of VMM topology choice, completely analyze the performance metrics, and describe the methods and tools involved in FPAA synthesis.

Rapid prototyping followed by technology retargeting provides a fast and cost-effective approach to analog system synthesis. Field-programmable analog arrays (FPAAs) enable rapid implementation of a function-compliant prototype, while technology retargeting converts the functional FPAA prototype to an ASIC. We first address the FPAA technology mapping problem. A novel structural approach based on hierarchical pattern matching and covering is employed to map the analog behavior onto the FPAA. We then address the issues of technology retargeting and design reuse, and present out FPAA-ASIC retargering strategy. We present experiments and a design example for FPAA technology mapping and retargeting.

Recent advances in embedded model predictive control (MPC) have paved the way for MPC technology in highspeed systems and resource-constrained applications. In this paper, we exploit analog circuit emulation of constrained Linear Quadratic (LQ) problem for rapid prototyping of MPC on fast reconfigurable analog processors such as Field Programmable Analog Arrays (FPAA). The inherent massively parallel structure of the underling solution dynamics and the possibility of signal scaling through appropriate pre-conditioning mean that MPC can be reliably implemented using low-power ultrafast analog circuits. The effectiveness of the approach is demonstrated for a two-integrator MPC problem.

For topography measurements and faster imaging with the AFM a high control-bandwidth is required. This paper presents an analog implementation of a model-based controller for a high-speed Atomic Force Microscope (AFM) using a new type of control hardware. The vertical positioning axis of the AFM scanner is modeled, and the imaging bandwidth is improved by means of model-based control. The new feedback controller, which is designed in the H <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∞</inf> -framework, is implemented on a Field Programmable Analog Array (FPAA), which enables operation of the model-based controlled AFM system at a feedback bandwidth on the order of 100 kHz. Measured results demonstrate that the closed-loop system recovers from a step-like disturbance within 7 microseconds. Recorded AFM images verify a significant performance improvement of the model-based controlled system over the analog proportional-integral (PI) controlled AFM.

Modern advances in reconfigurable technologies are allowing analog circuit designers to benefit from the computational flexibility provided by large-scale field-programmable analog arrays (FPAAs). With the component density of these devices, small analog circuits as well as larger analog systems can be synthesized and tested in a shorter time and at a lower cost compared to the full design cycle. However, automated development platforms and CAD tools for these devices are far fewer than the physical synthesis tools for their digital counterparts. One of the major reasons for this is the considerably higher impact of interconnect parasitics on circuit functionality in the analog domain; therefore, performance metrics must be monitored closely. Our goal in this paper is to present a physical synthesis framework with a generic architecture specification interface and a parasitic extractor for verification of the synthesis results. Our synthesis tool can support a wide range of FPAA architectures and our simulations can successfully predict the performance metrics.