A timing-driven soft-macro resynthesis method in interaction with chip floorplanning

A 128 K/spl times/8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-/spl mu/A standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-/spl mu/m twin-tub CMOS technology has been developed to realize the 5.6/spl times/9.5-/spl mu//SUP 2/ cell size and the 6.86/spl times/15.37-mm/SUP 2/ chip size.

We describe application-specific extensions for fuzzy processing to a general purpose processor. The application-specific instruction set extensions were defined and evaluated using hardware/software codesign techniques. Based on this approach, we have extended the MIPS instruction set architecture with only a few new instructions to significantly speed up fuzzy computation with no increase of the processor cycle time and with only minor increase in chip area. The processor is implemented using a reconfigurable processor core which was designed as a starting point for application-specific processor designs to be used in embedded applications. Performance is presented for three representative applications of varying complexity.

Long error detection latency, the time elapsed from the occurrence of an error caused by a bug to its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation and debug techniques. Traditional post-silicon validation tests can incur very long error detection latencies of millions or even billions of clock cycles. An earlier technique called Quick Error Detection (QED) shortens error detection latencies to only few hundred (or thousand) clock cycles. However, software-only QED (i.e., QED implemented entirely in software) can result in significantly increased post-silicon validation test runtimes. We present a new technique called Fast QED that overcomes this drawback of software-only QED, while preserving the error detection latency and bug coverage benefits of software-only QED. Simulation results using an OpenSPARC T2-like multi-core SoC and bugs abstracted from multiple commercial multi-core SoCs demonstrate: 1. Fast QED achieves 4 orders of magnitude improvement in test runtime as compared to software-only QED, with only 0.4% increase in chip area; 2. Fast QED improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error detection latencies compared to software-only QED; and, 3. Fast QED improves bug coverage by up to 2-fold compared to non-QED tests (similar to software-only QED).

Thermal hotspots are a destructive phenomenon occurring in contemporary microprocessors. High power density of microprocessors and excessive use of certain microprocessor components by applications are considered the primary causes of increased temperature. Dynamic Thermal Management Techniques used in mitigating excessive temperatures results in throttling of clock speed, which degrades the performance of the microprocessor. In this paper we propose a simple but novel technique to reduce hotspots in microprocessors. We propose to lower the power density of selected high temperature components by increasing the chip area of that component. We select thermally susceptible components that have small footprints and increase the area of such components, thereby reducing the occurrence of hotspots. The overall chip area increase is minimal and our research has shown that the associated delay penalty is negligible.

This study aims to examine the urgency, strategies, and problems in mastering the Arabic language for Islamic preaching communication. The focus of the research is on the students of the Faculty of Dakwah at Universitas Islam Negeri (UIN) Jakarta. Mastery of Arabic is considered crucial as it is the primary language of Islamic literature, which is fundamental to preaching activities. The research employs a qualitative method with a case study approach. Data were collected through interviews, observations, and documentation. The findings indicate that mastering Arabic is essential for enhancing understanding and effectively conveying Islamic messages. The strategies employed by students include formal classroom learning, self-study, and participation in extracurricular programs related to the Arabic language. However, students face various challenges, such as time constraints, lack of resources, and less varied teaching methods. The study recommends improving the quality of Arabic language teaching through more interactive methods and providing adequate resources to support learning. These findings provide insights for the development of a more effective Arabic language curriculum and learning strategies in Islamic higher education institutions.

In this paper, we propose a new and the first MCM system partitioning method considering chip-to-chip delays, chip areas and I/O pins constraints. The proposed method consists of two steps, a clustering step considering the three constraints and an iterative improvement step with mathematical programming. In the first step, we apply two clustering algorithms considering the three constraints and reduce the size of the large MCM system partitioning problem so as to get a solution within a practical computation time. Next, it generates an initial partitioning with 0-1 integer linear programming (ILP) so as to minimize the total wire length. Since there may exist constraint violations in the initial solution, in the second step, we formulate the partitioning problem as a LP problem selecting a maximal independent set and improve it until the total number of cuts is not decreased and the three constraints are satisfied. We also showed that the number of the timing constraints can be reduced by deleting redundant timing constraints. Experimental results showed that the proposed method is able to produce partitions satisfying the three constraints and improves the number of cuts by a 27% on an average and a 30% in maximum over the conventional method [15] considering only two constrains.

Optical lenses and systems have historically been of interest to the design and simulation community due to their extensive use in a variety of applications, including telecommunications and imaging. To simulate these systems, it is often possible to take advantage of symmetry or apply physical approximations, such as ray tracing and/or beam propagation, in order to avoid a rigorous solution of Maxwell's equations. However, in cases where these techniques are not applicable, such as when feature sizes become comparable to the wavelength of interest, full-wave electromagnetic simulations are required. Unfortunately, the time constraints and simulation sizes associated with many designs render this analysis infeasible or impractical, a problem that is aggravated by iterative design flows. Hence, a numerical platform capable of handling such computationally intense problems is necessary. In this paper, we present a hardware-based, full-wave simulation platform and demonstrate the advantages of hardware acceleration for the simulation of optical applications. Specifically, we will present a diffractive optical element (DOE) lens simulation, comparing results with previously published analytic and experimental data. We then modify the basic lens arrangement to produce an optical beam splitter. Because such a device cannot be analytically described using symmetry, this example will demonstrate the unique advantages of powerful hardware solvers for the analysis of DOE applications. Finally, we discuss how hardware-based solvers are critical for iterative designs by means of a 1-to-3 beam splitter example. This simulation system represents a new era in optical engineering, enabling the design of next-generation devices today.

The detailed timing information obtained from design iteration can only be added into synthesis process manually. A new strategy for automatic synthesis of backing marked timing information is presented in this paper. As the carrier of backing marked timing information, the delay statements in VHDL is synthesized in scheduling process. And a new scheduling algorithm is presented in this paper. The delay statements are considered to be delay time constraints by the algorithm. Scheduling data structure: DTC_DFG(delay time constrained data flow graph) is constructed and scheduled. A heuristic method is presented in this paper for the scheduling algorithm to jump out local optimization and reach global optimization under polynomial timing complexity. Experimental results are also presented in this paper. With the synthesis of delay statements, the backing marked timing information can be synthesized automatically, and the behavioral timing in design source can be synthesized directly, thus the timing consistency between synthesis result and simulation result can be improved. The delay statements then can be a convenient means to set timing constraints, thus the manual interruption in synthesis process can be decreased; the design efficiency can be improved greatly.

This study assessed the teaching strategies employed by lecturers to support learners with hearing impairments (LwHI) in higher learning institutions in Tanzania, addressing a critical gap in inclusive education practices. The research underscores the importance of adapting pedagogical approaches to promote equitable learning opportunities for all students. The study was guided by two objectives: (i) to examine the current teaching strategies utilized by lecturers in inclusive classrooms, and (ii) to explore the perceptions of LwHI regarding the effectiveness of these strategies. Employing a qualitative research approach within a single case study design, data were collected through semi-structured interviews with a purposive sample of 10 lecturers and 10 students with hearing impairments. The findings revealed that lecturers implemented a range of instructional strategies, including video captioning, transcription, sign language interpretation, visual aids, and the use of multimedia resources. Additionally, assistive technologies such as listening devices were employed alongside collaborative learning techniques. Despite these efforts, both lecturers and learners reported several challenges, including limited proficiency in assistive technology use, overcrowded classrooms, time constraints, and communication barriers due to unreliable interpretation services. The study recommends enhanced classroom modifications, targeted training for lecturers in sign language, and the increased application of interactive teaching methods. Furthermore, it calls on curriculum developers to integrate the specific needs of learners with hearing impairments into educational planning and instructional delivery.

We address the problem of timing constraint derivation and validation for reactive and real-time embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the system first to derive the timing constraints on the system's internal behavior and then use them to derive and validate the timing constraints on the system's external behavior. Our solution consists of the following contributions: a generalized task graph model, a comprehensive classification of timing constraints, algorithms for derivation and validation of timing constraints of the system modeled in the generalized task graph model, a codesign methodology that combines the model and the algorithms, and the implementation of this methodology in a tool called RADHA-RATAN. The main advantages of our solution are that it simplifies the problem of ensuring timing correctness of the system by reducing the complexity of the problem from system level to task level, and that it makes the codesign methodology timing-driven in that our solution makes it possible to maintain a handle on the system's timing correctness from very early stages in the system's design flow.

Advances in user interactivity in digital entertainment offer the potential to engage users beyond traditional passive and solitary experiences. Indeed, a high level of interactivity is inherent in tasks involving cooking, auto repair, and home improvement, all of which require users to complete multiple, detailed, and interdependent steps. Such tasks also require access to visual and audio instructions while a user's hands are engaged in a primary, physical task, and are often conducted in unique locations, e.g., kitchen or garage. This effort describes the design of an interactive, multimodal digital entertainment user experience for an ‘edutainment’ cooking show. The prototype wireframes incorporate three novel features, identified through requirements gathering and iterative design, of an interactive recipe map for hierarchical content navigation, voice command hands-free control, and avatars to further engage users. The overall design and three features were evaluated via usability testing in real kitchen settings in the conduct of actual cooking with real ingredients with a diverse range of seven participants. The results illustrate that the hierarchical navigational feature, alongside interactive voice communication, were effective at reducing users' cognitive load, and streamlined necessary information in order to support task completion.

Scalable hardware implementing high-radix Montgomery multiplication algorithm

A system level power/jitter reduction technique of all-digital phase locked loop (ADPLL) design has been developed. The architecture to memorize the repetitive control signal pattern of digitally-controlled oscillator (DCO) during lock state and to regenerate the pattern, achieve the reduced power consumption compared to conventional mode from 14.4 mW to 9.51 mW in 1.0 V supply at 12.2 GHz and concurrently reduce jitter from 1.86 ps to 1.56 ps. The prototype PLL has been fabricated in 65 nm CMOS process and occupies 0.16 ㎟ chip area.

History learning in the digital era requires teachers to adapt their teaching strategies to the characteristics of students who are accustomed to technological environments. This study aims to examine the challenges and strategies of history teachers in utilizing digital learning media at SMKN 1 Banjarmasin. The research employs a qualitative approach with a case study design. Data were collected through classroom observations, semi-structured interviews, and documentation. Informants consisted of two history teachers and ten students from grades X and XI who were directly involved in digital-based learning practices. The findings identified four main challenges: limited technological infrastructure, low digital competence among teachers, psychological barriers such as anxiety over technical disruptions, and time constraints due to administrative burdens. The strategies implemented by teachers included self-directed learning through online resources, peer collaboration, involving students in technical support, and using easily accessible digital media. In addition, some teachers integrated digital media with interactive methods such as quizzes and historical role-playing. These findings indicate that teachers are still able to innovate despite existing limitations. Future researchers are advised to further examine the effectiveness of these strategies on learning outcomes.

The peg-in-hole task with object feature uncertain is a typical case of robotic operation in the real-world unstructured environment. It is nontrivial to realize object perception and operational decisions autonomously, under the usual visual occlusion and real-time constraints of such tasks. In this paper, a Bayesian networks-based strategy is presented in order to seamlessly combine multiple heterogeneous senses data like humans. In the proposed strategy, an interactive exploration method implemented by hybrid Monte Carlo sampling algorithms and particle filtering is designed to identify the features’ estimated starting value, and the memory adjustment method and the inertial thinking method are introduced to correct the target position and shape features of the object respectively. Based on the Dempster–Shafer evidence theory (D-S theory), a fusion decision strategy is designed using probabilistic models of forces and positions, which guided the robot motion after each acquisition of the estimated features of the object. It also enables the robot to judge whether the desired operation target is achieved or the feature estimate needs to be updated. Meanwhile, the pliability model is introduced into repeatedly perform exploration, planning and execution steps to reduce interaction forces, the number of exploration. The effectiveness of the strategy is validated in simulations and in a physical robot task.