A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

We describe application-specific extensions for fuzzy processing to a general purpose processor. The application-specific instruction set extensions were defined and evaluated using hardware/software codesign techniques. Based on this approach, we have extended the MIPS instruction set architecture with only a few new instructions to significantly speed up fuzzy computation with no increase of the processor cycle time and with only minor increase in chip area. The processor is implemented using a reconfigurable processor core which was designed as a starting point for application-specific processor designs to be used in embedded applications. Performance is presented for three representative applications of varying complexity.

In this paper, we present a complete chip design method which incorporates a soft-macro resynthesis method in interaction with chip floorplanning for area and timing improvements. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs have demonstrated that by effectively relaxing the timing constraint of the non-critical modules and tightening the timing constraint of the critical modules, a design can achieve 13% to 30% timing improvements with little to no increase in chip area.

Long error detection latency, the time elapsed from the occurrence of an error caused by a bug to its manifestation as an observable failure, severely limits the effectiveness of existing post-silicon validation and debug techniques. Traditional post-silicon validation tests can incur very long error detection latencies of millions or even billions of clock cycles. An earlier technique called Quick Error Detection (QED) shortens error detection latencies to only few hundred (or thousand) clock cycles. However, software-only QED (i.e., QED implemented entirely in software) can result in significantly increased post-silicon validation test runtimes. We present a new technique called Fast QED that overcomes this drawback of software-only QED, while preserving the error detection latency and bug coverage benefits of software-only QED. Simulation results using an OpenSPARC T2-like multi-core SoC and bugs abstracted from multiple commercial multi-core SoCs demonstrate: 1. Fast QED achieves 4 orders of magnitude improvement in test runtime as compared to software-only QED, with only 0.4% increase in chip area; 2. Fast QED improves error detection latencies by up to 5 orders of magnitude compared to non-QED tests, and also achieves improved error detection latencies compared to software-only QED; and, 3. Fast QED improves bug coverage by up to 2-fold compared to non-QED tests (similar to software-only QED).

Thermal hotspots are a destructive phenomenon occurring in contemporary microprocessors. High power density of microprocessors and excessive use of certain microprocessor components by applications are considered the primary causes of increased temperature. Dynamic Thermal Management Techniques used in mitigating excessive temperatures results in throttling of clock speed, which degrades the performance of the microprocessor. In this paper we propose a simple but novel technique to reduce hotspots in microprocessors. We propose to lower the power density of selected high temperature components by increasing the chip area of that component. We select thermally susceptible components that have small footprints and increase the area of such components, thereby reducing the occurrence of hotspots. The overall chip area increase is minimal and our research has shown that the associated delay penalty is negligible.

Power-grid design is one of the key steps in achieving target performance of a modern System-on-Chip (SoC). With shrinking nodes the noise margin is reducing and hence it's imperative to have a robust power-grid. Power delivered to each design component in the layout directly impact the component delay, hence efficient power delivery is also an important requirement for the SoC. Current implementation tool's delay models don't take into account the effect of voltage-drop on the delays; hence, impact of voltage drop on performance is known only at the silicon. On the flip-side, over designing of the power grid will lead to routing congestion as well and may lead the increase in the chip area. Currently all the methods for the “early” power-grid is at the floorplan level, this is still late since, the chip size and area is committed to the customer, making a change here would be expensive and hence undesired. Methodology presented in this paper, with basic technology and design information will provide an optimal seed power-grid for a new design that would be correct by construct to achieve the desired performance goals, at the specification stage. Designer can add power-grid cost as part of the new chip analysis and predict the optimal area to meet the chip power requirements before floorplan stage. Experimental data shows a 35% average improvement in the routing utilization between the power-grid design based on the proposed methodology as compared to the traditional approach.

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.

We have developed a capacitive fingerprint sensor chip using low-temperature poly-Si thin film transistors (TFTs). We have obtained good fingerprint images which have sufficient contrast for fingerprint certification. The sensor chip comprises sensor circuits, drive circuits, and a signal processing circuit. The new sensor cell employs only one transistor and one sensor plate within one cell. There is no leakage current to other cells by using a new and unique sensing method. The output of this sensor chip is an analog wave and the designed maximum output level is almost equal to the TFT's threshold voltage, which is 2-3 V for low-temperature poly-Si TFTs. We used a glass substrate and only two metal layers to lower the cost. The size of the trial chip is 30 mm×20 mm×1.2 mm and the sensor area is 19.2 mm×15 mm. The size of the prototype cell is now 60 μm×60 μm at 423 dpi, but it will be easy to increase the resolution up to more than 500 dpi. The drive frequency is now 500 kHz and the power consumption is 1.2 mW with a 5-V supply voltage. This new fingerprint sensor is most suitable for mobile use because the sensor chip is low cost and in a thin package with low power consumption.

PurposeMajor area of a die is consumed in memory components. Almost 60-70% of chip area is being consumed by “Memory Circuits”. The dominant memory in this market is SRAM, even though the SRAM size is larger than embedded DRAM, as SRAM does not have yield issues and the cost is not high as compared to DRAM. At the same time, the other attractive feature for the SRAM is speed, and it can be used for low power applications. CMOS SRAM is the crucial component in microprocessor chips and applications, and as the said major portion of the area is dedicated to SRAM arrays, CMOS SRAM is considered to be the stack holders in the memory market. Because of the scaling feature of CMOS, SRAM had its hold in the market over the past few decades. In recent years, the limitations of the CMOS scaling have raised so many issues like short channel effects, threshold voltage variations. The increased thrust for alternative devices leads to FinFET. FinFET is emerging as one of the suitable alternatives for CMOS and in the region of memory circuits.Design/methodology/approachIn this paper, a new 11 T SRAM cell using FinFET technology has been proposed, the basic component of the cell is the 6 T SRAM cell with 4 NMOS access transistors to improve the stability and also makes it a dual port memory cell. The proposed cell uses a header scheme in which one extra PMOS transistor is used which is biased at different voltages to improve the read and write stability thus, helps in reducing the leakage power and active power.FindingsThe cell shows improvement in RSNM (read static noise margin) with LP8T by 2.39× at sub-threshold voltage 2.68× with D6T SRAM cell, 5.5× with TG8T. The WSNM (write static noise margin) and HM (hold margin) of the SRAM cell at 0.9 V is 306 mV and 384 mV. It shows improvement at sub-threshold operation also. The leakage power is reduced by 0.125× with LP8T, 0.022× with D6T SRAM cell, TG8T and SE8T. The impact of process variation on cell stability is also discussed.Research limitations/implicationsThe FinFet has been used in place of CMOS even though the FinFet has been not been a matured technology; therefore, pdk files have been used.Practical implicationsSRAM cell has been designed which has good stability and reduced leakage by which we can make an array and which can be used as SRAM array.Social implicationsThe cell can be used for SRAM memory for low power consumptions.Originality/valueThe work has been done by implementing various leakage techniques to design a stable and improved SRAM cell. The advantage of this work is that the cell has been working for low voltage without degrading the stability factor.

There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage current, dynamic power, and frequency as a function of supply voltage and body bias are derived and verified with SPICE simulation. Given these models, we show how to derive an analytical expression for the optimal trade-off between supply voltage and body bias, given a required clock frequency and duration of operation. The proposed method is then applied to a processor and is compared with DVS alone for workloads obtained using real-time monitoring of processor utilization for four typical applications.

BELLMAC-32A is a single-chip fully 32-bit high-end microprocessor designed in 2.5-?m twin-tub CMOS technology. This paper describes the gate matrix layout of random control logic in BELLMAC-32A with top-down hierarchical design methodology. The gate matrix layout provided (1) parallel team layout efforts, (2) adaptability to evolving logic design with short turnaround time, (3) high packing density competitive with hand layout, (4) compatibility with computer-aided layout and verification tools, (5) capability to fine-tune circuits, and (6) technology updatability. It took 6.5 engineer-years to complete the layout of random control logic with 7000 transistors although the logic design was continuously evolving during the layout period. The average packing density of gate matrix layout was 1500 ?m2 per transistor in random logic and 840 ?m2 per transistor in data path. BELLMAC-32A had more-than-three times performance improvement over its 3.5 ?m technology prototype chip BELLMAC-32, in which random control logic was implemented with polycells.

This paper demonstrates the 32-Mb chain ferroelectric RAM (chain FeRAM) with 0.2-μm three-metal CMOS technology. A small die size of 96 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a high cell/chip area efficiency of 65.6% are realized not only by the small cell size using capacitor-on-plug technology but also by two key techniques that utilize the three-metal process: 1) a compact memory cell block structure that eliminates plateline area and reduces block selector area and 2) the segment/stitch array architecture which reduces the area of row decoders and plate drivers. As a result, the average cell size shrinks to 1.875 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is smaller than a 0.13-μm SRAM cell, and the chip size is reduced to 70% of the chain FeRAM of conventional configuration with two-metal process. Moreover, a power-on/off sequence suitable to the chain FeRAM is introduced to protect the memory cell data from the startup noise. Compatibility with low-power SRAM is a key issue for mobile applications. The low-standby-current bias generator is introduced and the standby current of the chip is suppressed to 3 μA. The modified address access mode is also adopted to eliminate the need of intentional address transition after the startup of the chip. The chip enable access time was 50 ns and cycle time was 75 ns at 3.0-V V/sub dd/.

We present an experimental study of the transport properties (low field hole mobility /spl mu//sub h/) and electrostatics (threshold voltage V/sub th/, and gate-to-channel capacitance C/sub gc/) of ultrathin body (UTB) SOI pMOSFETs using a large RingFet structure. Body thicknesses were /spl sim/4.3 nm to 50 nm. We find that 1) hole mobility decreases significantly as T/sub Si/<10 nm, and tends to show negligible dependence on the transverse electric field for extremely thin T/sub Si/ (<6 nm) and 2) a V/sub th/ shift of /spl sim/150 mV occurs over the studied T/sub Si/ range, accompanied by enhancement of weak inversion capacitance in thin body devices. Simulations were performed to provide insight into the experimental observations.

The effects of DC hot-carrier stress on DC and RF performance of submicron LDD NMOSFETs are investigated. It is shown that transit frequency f/sub T/ decreases as transconductance g/sub m/ of the transistor is degraded with stress but it is observed that degradation of f/sub T/ versus stress time is faster than that of g/sub m/. This was found to be due to the increase of the gate-source capacitance C/sub gs/ with stress. Threshold voltage V/sub th/ and output conductance g/sub ds/ increase and voltage gain of the device /spl mu//sub f/ decreases with stress. Stability factors K and /spl Delta/ also change toward higher stability with stress.

A novel Under Voltage Lockout (UVLO) circuit featuring with fast response speed and low temperature coefficient threshold voltages is proposed in this paper. Compared with the conventional structure, the proposed circuit achieves the fast response ability thanks to the current-mode control technique is utilized. Meanwhile, this UVLO realizes hysteretic threshold by a feedback control path to improve the interference rejection capability. In addition, the threshold voltage varies slightly with the variation of the supply voltage and temperature by using a bandgap core. The proposed circuit implemented with 0.5μm BCD technology has an input high threshold voltage of 8.5V and a hysteresis of 1.5V, and start or shut off the power quickly. Test results verified that the proposed UVLO has the qualification to be applied to DC-DC converters.

VLSI computing is critical in chip fabrication in today's digital age. Moore's law demands that "the number of transistors on a microchip doubles every two years" in addition to that "the count of transistors employed in a chip size is reduced". As a result, this rule is dictating the electronics industry by reducing chip area, size, and power consumption while simultaneously enhancing chip fabrication strength. The arithmetic circuits are constructed in this work, by boosting the efficiency of circuits by considering die space as a constraint. Overall, arithmetic circuits have a bunch of usages in processing architecture. The XOR gate and multiplexer are utilized in this study to make compressor circuits more efficient by taking into account area, power, and delay. To examine the arithmetic circuit's performance, the load capacitance is customized and the power dissipation across the capacitor is studied.