A zero power consumption Multi-Capacitor structure for voltage summing in high-speed FFE

Electromagnetic interference (EMI) signals, which radiate in the environment and cause the malfunction of electronic devices in proximity, are generated due to the common mode (CM) noise in differential circuits. This CM noise is produced because of the imbalance in the charging and discharging paths of the driver and equalizer circuits in the transmitter. However, the effects of the equalizer on CM noise have not been examined. This paper systematically investigates the effect of different feed forward equalizer (FFE) configurations on EMI-related CM noise in a 56-Gbps four-level pulse-amplitude modulation (PAM-4) optical transmitter, aiming to provide an optimized configuration with low CM noise and power consumption, while providing high compensation. The simulation results show that an asymmetric equalizer significantly improves the compensation performance. However, the offset in differential pair of output stage should be minimized to decrease the CM noise generated from the FFE.

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface

Experimental demonstration of 25-Gb/s downstream transmission using 10-Gbps optics for next-generation PONs

This paper presents a high-speed, large-output swing driver with 2-tap feed-forward equalizer (FFE) for optical modulators in 130-nm SiGe BiCMOS process. A breakdown voltage (BV) doubler topology with all-pass filter (APF)-based dynamic bias is applied in the driver to improve the output swing and the bandwidth. A 2-tap fractional-spaced FFE is implemented to compensate for the insufficient bandwidth of optical modulators. Simulation results indicate that the driver achieves an output swing of 4 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{v}_{\text{ppd}}$</tex> and a 3-dB bandwidth of 62.4 GHz with a power consumption of 1.15 W. The performance of the driver is further evaluated in an electrical/optical (E/O) system where a Verilog-A model for Mach-Zehnder Modulator (MZM) with a 3-dB bandwidth of 35 GHz is used. Taking advantages of the 2-tap FFE, the E/O system achieves a 3-dB bandwidth of 50.4 GHz and can support 160-Gb/s PAM-4 optical communications.

A hybrid integrated 16-channel silicon transmitter based on co-designed photonic integrated circuits (PICs) and electrical chiplets is demonstrated. The driver in the 65 nm CMOS process employs the combination of a distributed architecture, two-tap feedforward equalization (FFE), and a push–pull output stage, exhibiting an estimated differential output swing of 4.0Vpp. The rms jitter of 2.0 ps is achieved at 50 Gb/s under nonreturn-to-zero on–off keying (NRZ-OOK) modulation. The PICs are fabricated on a standard silicon-on-insulator platform and consist of 16 parallel silicon dual-drive Mach–Zehnder modulators on a single chip. The chip-on-board co-packaged Si transmitter is constituted by the multichannel chiplets without any off-chip bias control, which significantly simplifies the system complexity. Experimentally, the open and clear optical eye diagrams of selected channels up to 50 Gb/s OOK with extinction ratios exceeding 3 dB are obtained without any digital signal processing. The power consumption of the Si transmitter with a high integration density featuring a throughput up to 800 Gb/s is only 5.35 pJ/bit, indicating a great potential for massively parallel terabit-scale optical interconnects for future hyperscale data centers and high-performance computing systems.

Aiming at the problem of signal integrity degradation caused by transmission channel loss in high-speed serial links (SerDes) at a data rate of $\mathbf{1 6 ~ G b p s}$, this paper designs a SerDes transmitter (TX) equalizer that complies with the PCIe 4.0 protocol standard. This feed-forward equalizer (FFE) mitigates high-frequency channel attenuation via pre-emphasis techniques and employs a source-series terminated (SST) driver architecture to realize low-noise and low-reflection output characteristics. The circuit design was fully implemented based on a 16 nm FinFET process. Simulation results demonstrate that under the transmission scenario of a transmission line with an equivalent characteristic impedance of 50 ohms, the eye height of the differential output signal of the transmitter reaches 623 mV, the eye width reaches 31.24 ps, and the jitter of 1.09 ps is less than 0.035 UI, which meets the requirements of the PCIe 4.0 protocol; the power consumption test shows that the total power consumption during operation is $\mathbf{3 2 ~ m W}$.

Optical communication networks (OCNs) provide promising and cost-effective support for the ultra-fast broadband solutions, thus enabling them to address the ever growing demands of telecommunication industry such as high capacity and end users’ data rate. OCNs are used in both wired and wireless access networks as they offer many advantages over conventional copper wire transmission such as low power consumption, low cost, ultra-high bandwidth, and high transmission rates. Channel effects caused by light propagation through the fiber limits the performance, hence the data rate of the overall transmission. To achieve the maximum performance gain in terms of transmission rate through the OCN, an optical downlink system is investigated in this paper using feed forward equalizer (FFE) along with decision feedback equalizer (DFE). The simulation results show that the proposed technique plays a key role in dispersion mitigation in multi-channel optical transmission to uphold multi-Gb/s transmission. Moreover, bit error rate (BER) and quality factor (Q-factor) below 10 − 5 and above 5, respectively, are achieved with electrical domain equalizers for the OCN in the presence of multiple distortion effects showing the effectiveness of the proposed adaptive equalization techniques.

An analog feed forward error equalizer (AFFE) is described that cancels precursor intersymbol interferences (ISI) in the front end of gigabit Ethernet on twisted pair interfaces. Forward equalizing in analog domain not only reduces the complexity and area of digital forward equalizer, but also leads to lower power consumption and higher speed. The proposed equalizer, based on five taps discrete time filtering, is designed in a 0.18mum CMOS technology. The design operates at 125MHz while consuming 38mW from a 1.8V supply. The low power and high speed design is achieved by implementation of each filter tap only by an improved Gilbert cell instead of using a multiplier for each bit of the filter tap which consumes more area and power and affected by switches noise and clock jitter too. Moreover S/H power and speed requirements are relaxed by using a redundant S/H and an additional clocking phase

For serial wireline communication beyond 56 Gb/s, bandwidth-efficient modulation is needed. Four-level pulse amplitude modulation (4-PAM) has become the standard technique at 56–64 and 112 Gb/s. However, whereas decision feedback equalization (DFE) with 5 taps or more was common for 2-PAM links at lower data rates, the speculative look-ahead techniques required to satisfy a DFE's timing requirements at 56 Gb/s increase power consumption exponentially with the number of taps and the number of modulation levels. Thus, 4-PAM DFEs at 56 Gb/s are generally limited to 2 taps or fewer. This limitation, in turn, necessitates the use of long (10 taps or more) finite impulse response (FIR) feed-forward equalization (FFE) to accurately eliminate the intersymbol interference in long reach (LR) channels. Thus, LR receivers at 56–64 and 112 Gb/s comprise an analog-to-digital converter (ADC) followed by digital equalization, and the transmitters increasingly use a digital-to-analog converter (DAC) preceded by a digital filter. Discrete multitone (DMT) signalling obviates the need for a long FIR FFE and DFE, and has demonstrated better spectral efficiency than 4-PAM above 50 Gb/s. In this work, we consider the potential of DMT for wireline communication beyond 100 Gb/s. For example, a spectral efficiency of 2.5 bits/sample is achievable over an IEEE P802.3ck channel with 18 dB loss at 40 GHz, affording an aggregate data rate of 200 Gb/s at 80 GS/s with 150 fs of jitter and 1.26 mV of noise at the input to the receiver. Significant improvement in bit error rate (BER) is obtained by increasing DAC resolution to 8 bits.

A 224-Gb/s pulse amplitude modulation 4-level (PAM4) ADC-based SerDes receiver (RX) is implemented in a 5-nm FinFET process. The RX consists of a low-noise hybrid analog front-end (AFE) that incorporates both inductive peaking and source degeneration, a 64-way time-interleaved ADC, digital equalization consisting of an up to 30 tap feed-forward equalizer (FFE), optional decision-feedback equalizer (DFE), and a clock-data-recovery (CDR) loop utilizing a 14-GHz digitally controlled oscillator (DCO). The RX was characterized for medium-to-long reach channels (20.6-, 27-, 31.4-, and 38-dB insertion loss at Nyquist) with a corresponding pre-forward error correction (FEC) bit error rates of 1.9E-11, 5.2E-10, 1.2E-8, and 6E-7, respectively. The analog power consumption of the RX is 1.41 pJ/b.

Photonic computing and signal processing are rapidly regaining attention, capitalizing on the saturation of digital electronics capabilities, owed to the ending of the Moore's law era. Optical communications are among the fields in which digital signal processing (DSP) struggles to offer a viable long-term solution, as its power consumption rises significantly in the latest generation optical links. For example, the traditional intensity modulation and direct detection (IM/DD) systems suffer from challenging problems such as the chromatic dispersion induced power fading effect, which necessitates the use of powerful digital equalizers in the 800G and 1.6T optical transceivers. Here, we experimentally validate our previous numerical works in recurrent optical spectrum slicing (ROSS) accelerators for dispersion compensation in IM/DD links. For this, we utilize recurrent filters implemented both through a waveshaper and by exploiting novel programmable photonic platforms. The ROSS accelerators exploit frequency processing in order to mitigate the power fading effect, which hinders the scalability of IM/DD systems. By equalizing even 80 km of 64 Gb/s PAM-4 transmission in C-band, we prove that our system can offer an appealing solution in highly dispersive channels. We employ the simplest digital equalization in the form of a feed-forward equalizer (FFE), avoiding throughput, latency, and complexity restrictions other digital equalizers impose. We achieve to reduce the bit error rate (BER) from 0.11 to less than 1 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup> with the use of only two filter nodes, whereas BER approaches 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> when three nodes are incorporated. These results correspond to almost two orders of magnitude BER gain.

This paper presents a 2-40 Gb/s dual-mode wireline transmitter supporting the four-level pulse amplitude modulation (PAM4) and non-return-to-zero (NRZ) modulation with a multiplexer (MUX)-based two-tap feed-forward equalizer (FFE). An edge-acceleration technique is proposed for the 4:1 MUX to increase the bandwidth. By utilizing a dedicated cascode current source, the output swing can achieve 900 mV with a level deviation of only 0.12% for PAM4. Fabricated in a 65-nm CMOS process, the transmitter consumes 117 mW and 89 mW at 40 Gb/s in PAM4 and NRZ at 1.2 V supply. © 2018, Institute of Electronics Engineers of Korea. All rights reserved.

The DRAM interface development to achieve a higher bandwidth has been requested according to the advance in massive computing technologies. Multi-level signaling, PAM-4 for example, is one of the most promising ways to address the requirement to extend the per-pin data rate without increasing clock frequency [1]. This paper suggests a single-ended PAM-4 transmitter for DRAM interface which requires high-speed operation. A 4-to-1 MUX based 2-tap feedforward equalizer (FFE) for bandwidth extension is used to mitigate the channel loss and inter-symbol interference (ISI). The impedance of each PAM-4 signal level can be controlled separately by applying thermometer switching in the main driver to achieve precise matching. The output driver of PAM-4 transmitter is optimized to have high linearity for operation of both low-voltage swing terminated logic (LVSTL) and pseudo open drain (POD). Also, a new timing skew training scheme for each PAM-4 signal level is developed to adjust timing for reducing clock skew in the internal path caused by PVT variations and bit error ratio (BER) increased by the non-linear characteristics of receiver. In addition, low power maximum transition avoidance (LPMTA) encoding is applied to decrease energy consumption of output driver. The prototype chip is fabricated in a 28nm CMOS process with adjusted channel length, not applying a minimum channel length, to mimic 10nm class DRAM process conditions. It is confirmed that propagation delay time (TPD) and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathrm{I}_{\text{dsat}}$</tex> of prototype chip are well correlated with the parameters obtained by 10nm class DRAM process. Finally, 1.67-pJ/b of energy efficiency with 1.2V supply is measured at 60-Gb/s/pin with optimized single-ended PAM-4 transmitter.

A standard CMOS optical interconnect is proposed, including an octagonal-annular emitter, a field oxide, metal 1-PSG/BPSG-metal 2 dual waveguide, and an ultra high-sensitivity optical receiver integrated with a fingered P+/N-well/P-sub dual photodiode detector. The optical interconnect is implemented in a Chartered 3.3-V 0.35-μm standard analog CMOS process with two schemes for the research of the substrate noise coupling effect on the optical interconnect performance: with or without a GND-guardring around the emitter. The experiment results show that the optical interconnect can work at 100 kHz, and it is feasible to implement optical interconnects in standard CMOS processes.