Asynchronous Sampling-Based Hybrid Equalizer

A 25-Gb/s half-rate clock and data recovery (CDR) IC using a current-mode logic (CML) buffer circuit with a latch load circuit for delay generation is presented. To achieve low-power operation of the CDR, the latch-load circuit for delay generation is combined with a CML buffer circuit, which provides a wide controllable delay range. This enable a reduction in the number of the CML circuits for delay generation used in the CDR IC. To confirm the validity of the proposed method, we fabricated a 25-Gb/s half-rate CDR IC with the 65-nm CMOS process. The power consumption of the proposed circuit is around half that of the conventional half-rate CDR circuit The area for the core circuits is 0.09 mm2, and the power consumption without output buffers is 96mW.

This article presents a 56-Gb/s distributed feedback (DFB) laser driver integrated with a PAM-4 clock and data recovery (CDR). A mixed-signal digital-to-analog converter (DAC) is adopted for power-efficient linear driving. With the help of the CDR, high-speed PAM-4 input is digitized into thermometer code, which is processed in NRZ format along the data path before summation at the output node. In this way, higher modulation linearity is realized by independently adjusting the weight of each slice. A dc-coupled differential drive stage is devised to improve signal integrity and energy efficiency at high speed. Employing a fractional-UI delay asymmetric feed-forward equalization (FFE) extends the laser’s bandwidth while the nonlinearity is compensated. The proposed driver is fabricated in 28-nm CMOS and co-packaged with a DFB laser diode. Measurement results show the modulated optical output reaches a 56-Gb/s data rate and consumes 353-mW power, thus corresponding to the energy efficiency of 6.3 pJ/bit, including the integrated CDR.

This paper presents a programmable half-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O links. The CDR is implemented in TSMC 28nm high-k metal-gate CMOS technology and covers a continuous range of data rates from 2.5Gb/s to 12.5Gb/s. The higher data rate is achieved by demultiplexing and decimating the sampled data in order for the subsequent circuit to operate at a much lower speed. The CDR is able to track maximum frequency deviation of ±286.78 ppm between the incoming data and the local reference clock at 12.5Gb/s. The CDR occupies a chip area of 18700um2 and consumes 30.30mW of power at 12.5Gb/s.

The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC - DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high - loss links. Typically, a continuous-time linear equalizer (CTLE) and a multi-tap decision-feedback equalizer (DFE) are implemented in a mixed-signal receiver (RX). However, when the data rate reaches 112Gb/s, the implementation of the DFE suffers from stringent feedback timing. Direct DFE works only at 100Gb/s in an optical receiver [1], leaving no room for feedforward error correction (FEC). A speculative 1 - tap DFE is implemented in [2], but it requires an 8-tap feedforward equalizer (FFE) at the transmitter (TX) to generate a 1+0.5D response; this may be impractical without knowing the characteristics of the entire channel. Another drawback of a speculative DFE is the large 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -tap latency, which brings about challenges in realizing two or more taps. In addition, the DFE does not compensate for pre-cursor inter-symbol interference (ISI), which becomes significant for channels with higher loss. Without a DFE, the CTLE only covers a small loss of up to 10dB [3,4]. This paper presents a 112Gb/s mixed-signal transceiver using an RX analog FFE with adaptive pre- and post-cursor ISI equalization in 28nm CMOS, compensating for 20.8dB loss at a power efficiency of 2.29pJ/b.

Skin effect and dielectric loss in super-long cable will cause nonlinear attenuation at different signal frequency, and in addition, coupling noise and thermal noise also cause signal distortion at the receiver end. These factors seriously affect the signal transmission speed in the super-long cable. Especially, in the field of exploration of shale gas and bed methane, the transmission cable is also used to transport high-precision synchronization pulse signal, and the synchronization pulse must reach the microsecond accuracy, which is used for data phase calibration. A synchronization signal is a high frequency signal, which suffers more severe attenuation and noise interference. At the receiving end, the sync pulse signal will be drowned in the noise environment, and so it is difficult to restore the original signal.#br#Although fiber can achieve a high transfer rate, but the fiber cable cannot transmit power energy; in addition, the tensile strength and heat resistance of the fiber are much worse than copper cable, these weaknesses limit its application in such industry. Therefore, an effective balancing algorithm is necessary to overcome the propagation effects and interference in a super-long copper cable. However, conventional equalization techniques have well-balanced effect for the short-range communications, but for the long-distance communication, they often have poorly balanced results. In order to solve the above problem and improve the long cable signal transmission speed, this paper presents a new balanced portfolio structure; the new structure uses feed-forward equalizer (FFE) as the pre-stage, and decision-feedback equalizer (DFE) as the post stage to form a new structure. The combination structures can effectively utilize the flexibility of FFE and overcome the problem of error diffusion in DFE. By mathematical modeling and simulation, this paper gives the best combination factors. Furthermore, based on the improved structure, a new convergence algorithm is proposed, which uses the arc tangent function combined with three error converge factors to form a converging function, and it has the advantages of fast convergence and steady-state error. Simulation results show that the FFE-DFE combination equalizer has low computational complexity, fast convergence, and strong channel tracking capability; in addition, it can speed up the data processing speed, and better respond to the real variation of the channel. Simulation results show also that the performance is improved by 50% by eliminating inter-symbol interference and noise.#br#The real circuit board based on the new algorithm have been tested in the East China Petroleum Bureau, the test results show that the algorithm can rectify 160 dB signal distortion, and the transmission speed can reach 5 Mbps in 6 dB signal to noise ratio.

This paper presents a power and area efficient approach to embed a continuous-time linear equalizer (CTLE) within a clock and data recovery (CDR) circuit implemented in 65-nm CMOS. The merged equalizer/CDR circuit achieves full-rate operation up to 28 Gb/s while drawing 104 mA from a 1-V supply and occupying 0.33 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Current-mode-logic (CML) circuits with shunt peaking loads using customized differential pair layout are used to maximize circuit bandwidth. To minimize the area penalty, differential stacked spiral inductors (DSSIs) are employed extensively. A novel and practical methodology is introduced for designing DSSIs based on single-layer inductors provided in foundry process design kits (PDK). The DSSI design increases the inductance density by over 3 times and the self-resonance frequency by 20% compared to standard single-layer inductors in the PDK. The measured BER of the recovered data by the CDR is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> at 27 Gb/s for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> -1 400 mV PP pseudo-random binary sequence (PRBS) as input data. The measured rms jitter of the recovered clock and data are 1.0 and 2.6 ps, respectively. The CDR is able to lock to inputs ranging from 26 to 28 Gb/s with 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> -1 PRBS pattern. Measurement results show that with the equalizer enabled, the CDR can recover a 26-Gb/s 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> -1 PRBS data with BER ≤ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> after a channel with 9-dB loss at 13 GHz.

For serial wireline communication beyond 56 Gb/s, bandwidth-efficient modulation is needed. Four-level pulse amplitude modulation (4-PAM) has become the standard technique at 56–64 and 112 Gb/s. However, whereas decision feedback equalization (DFE) with 5 taps or more was common for 2-PAM links at lower data rates, the speculative look-ahead techniques required to satisfy a DFE's timing requirements at 56 Gb/s increase power consumption exponentially with the number of taps and the number of modulation levels. Thus, 4-PAM DFEs at 56 Gb/s are generally limited to 2 taps or fewer. This limitation, in turn, necessitates the use of long (10 taps or more) finite impulse response (FIR) feed-forward equalization (FFE) to accurately eliminate the intersymbol interference in long reach (LR) channels. Thus, LR receivers at 56–64 and 112 Gb/s comprise an analog-to-digital converter (ADC) followed by digital equalization, and the transmitters increasingly use a digital-to-analog converter (DAC) preceded by a digital filter. Discrete multitone (DMT) signalling obviates the need for a long FIR FFE and DFE, and has demonstrated better spectral efficiency than 4-PAM above 50 Gb/s. In this work, we consider the potential of DMT for wireline communication beyond 100 Gb/s. For example, a spectral efficiency of 2.5 bits/sample is achievable over an IEEE P802.3ck channel with 18 dB loss at 40 GHz, affording an aggregate data rate of 200 Gb/s at 80 GS/s with 150 fs of jitter and 1.26 mV of noise at the input to the receiver. Significant improvement in bit error rate (BER) is obtained by increasing DAC resolution to 8 bits.

Phase-locked loop (PLL) based clock and data recovery (CDR) circuits use a 2x-oversampling (2XO) of the incoming non-return to zero (NRZ) data stream to recover the data. As an extension of the idea, 3x-oversampling (3XO) CDR circuits provide improved performance in the presence of total asymmetric jitter. This paper presents an overview of the oversampling CDR circuits with an emphasis on digital architectures. These include, but are not limited to, the 3XO jitter-tolerant variable-interval 3XO architecture, the 3XO eye-tracking architecture, and the blind oversampling architecture. We propose a modified architecture that utilizes multiple rotating phases to improve the performance of the 3XO eye-tracking architecture

This paper presents a forwarded-clock receiver (RX) that consists of a weight-adjusting sign-sign Mueller-Müller clock and data recovery (CDR) and an adaptive decision-feedback equalizer (DFE) with a single shared error sampler. Only two samples per bit are utilized for both CDR and adaptive DFE, which minimizes clocking power consumption. In addition, a maximum-eye tracking algorithm is proposed to enhance the vertical eye margin without any extra high-speed analog circuitry. The RX fabricated in a 28nm CMOS technology achieves BER less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> with a 20dB-loss channel. It occupies an active area of 0.108 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and consumes 56.65 mW at 28 Gb/s.

Optical communication networks (OCNs) provide promising and cost-effective support for the ultra-fast broadband solutions, thus enabling them to address the ever growing demands of telecommunication industry such as high capacity and end users’ data rate. OCNs are used in both wired and wireless access networks as they offer many advantages over conventional copper wire transmission such as low power consumption, low cost, ultra-high bandwidth, and high transmission rates. Channel effects caused by light propagation through the fiber limits the performance, hence the data rate of the overall transmission. To achieve the maximum performance gain in terms of transmission rate through the OCN, an optical downlink system is investigated in this paper using feed forward equalizer (FFE) along with decision feedback equalizer (DFE). The simulation results show that the proposed technique plays a key role in dispersion mitigation in multi-channel optical transmission to uphold multi-Gb/s transmission. Moreover, bit error rate (BER) and quality factor (Q-factor) below 10 − 5 and above 5, respectively, are achieved with electrical domain equalizers for the OCN in the presence of multiple distortion effects showing the effectiveness of the proposed adaptive equalization techniques.

A 10 Gb/s adaptive analog decision feedback equalizer (DFE) with 6 taps is realized in 0.13 μm CMOS. A modified Cherry-Hooper stage is designed as the delay element in the feed-forward path. An analog implementation of the LMS algorithm is used to continuously adapt the feedback filter coefficients. A clock and data recovery (CDR) circuit is used to extract the clock from the DFE output. The adaptive DFE dissipates 452 mW and can equalize PRBS data corrupted by a 300m-long multimode fiber (MMF) achieving BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .

Clock and data recovery (CDR) circuit in general, plays a vital role for serial-link communication in multi-module based System on chip (SOC). It uses a high frequency clock to handle high data rate, which results in high dynamic power consumption. In order to reduce the high dynamic power consumption, the proposed design works at the one-eighth frequency of the received data rate and presents a novel digital octa-rate clock and data recovery circuit as an optimal solution. The octa-rate CDR circuit consists of 16-phases generator, delay line controller, an octa-rate early-late type phase detector and digitally controlled delay line. The purpose of delay line controller is to provide sufficient delay in digitally controlled delay line. It is observed from literature that the existing delay line controller is realized by using combinational circuit which is not providing sufficient delay. Hence, in this work we introduced Finite State Machine (FSM) based delay line controller to provide sufficient delay. In order to reduce dynamic power consumption, a novel octa-rate CDR circuit has been realized using Xilinx ISE 13.2 and implemented on Vertex-5 FPGA target device for real time verification. Corresponding results shows a significant dynamic power reduction.

Rapid internet traffic growth has fueled the demand for bandwidth in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impairments at 25Gb/s with up to 30dB loss at Nyquist, a feed-forward equalizer (FFE)/decision feedback equalizer (DFE) based transceiver without power-hungry analog-to-digital converter (ADC) provides robust performance. This work presents a low-power and area-efficient transceiver that employs a 14-tap adaptive DFE at the receiver (RX) and a 5-tap FFE at the transmitter (TX) for multi-standard applications up to 28Gb/s in 28nm CMOS.

A 224-Gb/s pulse amplitude modulation 4-level (PAM4) ADC-based SerDes receiver (RX) is implemented in a 5-nm FinFET process. The RX consists of a low-noise hybrid analog front-end (AFE) that incorporates both inductive peaking and source degeneration, a 64-way time-interleaved ADC, digital equalization consisting of an up to 30 tap feed-forward equalizer (FFE), optional decision-feedback equalizer (DFE), and a clock-data-recovery (CDR) loop utilizing a 14-GHz digitally controlled oscillator (DCO). The RX was characterized for medium-to-long reach channels (20.6-, 27-, 31.4-, and 38-dB insertion loss at Nyquist) with a corresponding pre-forward error correction (FEC) bit error rates of 1.9E-11, 5.2E-10, 1.2E-8, and 6E-7, respectively. The analog power consumption of the RX is 1.41 pJ/b.

A bang-bang half-rate architecture is presented for high-speed random input clock and data recovery. In contrast to the conventional half-rate architectures, which contain two separated full-rate phase detectors and additional complicated logic and clock distribution circuits, the proposed architecture utilizes a genuine half-rate phase detector and eliminates the logic circuits. Therefore, it significantly simplifies the circuit complexity. A SiGe clock and data recovery circuit using this architecture is designed with 40Gb/s input data rate.