The novel feed forward and decision feedback equalizer structures and improved variable step algorithm

The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC - DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high - loss links. Typically, a continuous-time linear equalizer (CTLE) and a multi-tap decision-feedback equalizer (DFE) are implemented in a mixed-signal receiver (RX). However, when the data rate reaches 112Gb/s, the implementation of the DFE suffers from stringent feedback timing. Direct DFE works only at 100Gb/s in an optical receiver [1], leaving no room for feedforward error correction (FEC). A speculative 1 - tap DFE is implemented in [2], but it requires an 8-tap feedforward equalizer (FFE) at the transmitter (TX) to generate a 1+0.5D response; this may be impractical without knowing the characteristics of the entire channel. Another drawback of a speculative DFE is the large 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -tap latency, which brings about challenges in realizing two or more taps. In addition, the DFE does not compensate for pre-cursor inter-symbol interference (ISI), which becomes significant for channels with higher loss. Without a DFE, the CTLE only covers a small loss of up to 10dB [3,4]. This paper presents a 112Gb/s mixed-signal transceiver using an RX analog FFE with adaptive pre- and post-cursor ISI equalization in 28nm CMOS, compensating for 20.8dB loss at a power efficiency of 2.29pJ/b.

For mild and severe nonlinear distortions in digital communication systems, this paper analyses Chebyshev orthogonal polynomial neural network nonlinear filter, combines the structure of simplified nonlinear filter, and extends decision feedback equalizer's structure with characteristics of decision feedback equalizer (DFE)'s structure. A novel structure of conjunction decision feedback equalizers is proposed, and adaptive algorithm is deduced with the normalized LMS (NLMS). Computer simulations show that not only the new type structure equalizer is simpler structure and but also can availably remove nonlinear's distortions and ISI, improve performance of BER no matter what mild or serve nonlinear distortions

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

This paper presents the experimental characterization of a High-Speed Serial Interface (HSSI) for automotive microcontroller applications designed in 28 nm planar CMOS technology, verified over automotive corners and operating up to 11 Gb/s. The impedance of the full-rate voltage-mode transmitter can be tuned by activating several driver replicas. It also features an 8-tap Feed-Forward Equalizer (FFE) with taps programmable in steps of 1/16. The analog front-end of the receiver cascades a Variable-Gain Amplifier (VGA) and a Continuous-Time Linear Equalizer (CTLE), which can be individually tuned. The receiver is based on a half-rate architecture and features a 3-tap Decision-Feedback Equalizer (DFE), one tap being speculative to relax timing constraints; another VGA is embedded in the DFE summing node. The subsequent data and edge samplers are offset-compensated. The circuit is experimentally characterized over automotive corners at 6.25 Gb/s and 11 Gb/s on highly-reflecting PCB channels with up to 14.5 dB loss, demonstrating operations at bit-error ratio (BER) below 10−12 up to 11 Gb/s. The HSSI occupies an area of 0.08 mm2 and consumes 8.4 mW/Gb/s at 11 Gb/s and 6.2mW/Gb/s at 6.25 Gb/s.

Rapid internet traffic growth has fueled the demand for bandwidth in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impairments at 25Gb/s with up to 30dB loss at Nyquist, a feed-forward equalizer (FFE)/decision feedback equalizer (DFE) based transceiver without power-hungry analog-to-digital converter (ADC) provides robust performance. This work presents a low-power and area-efficient transceiver that employs a 14-tap adaptive DFE at the receiver (RX) and a 5-tap FFE at the transmitter (TX) for multi-standard applications up to 28Gb/s in 28nm CMOS.

Addresses problems related to the conceptual design of a fully digital synchronous DFE (decision feedback equalizer) and investigates the effects of the necessary quantization of the input signals and coefficients on DFE performance in static and dynamic operation. The analysis is performed taking into account the following topics: the influence of the dynamic range and quantization levels of the input signal and coefficients: the tracking and acquisition algorithm capabilities; comparison of DFE structures; and the extension of robust algorithms to DFEs. An experimental setup including a digital baseband equalizer is described. Results are reported for two kinds of DFE structures and a 16-AQM (quadrature amplitude modulation) modulation format. Specific problems related to the operation of DFEs in digital radio modems are discussed. It is established that the DFE structure is able to track continuous minimum-phase to nonminimum-phase transitions and vice versa without getting out of lock. This is an important result since the DFE outperforms current linear equalizers. >

We illustrate a new type of nonlinear obtained by placing a decision feedback and a decision feedforward in parallel. This type of called a parallel decision feedback and feedforward equalizer or, briefly, a equalizer, is characterized by substantially reduced error propagation if the eye diagram is open at the input of the decision device of the decision feedback and of the first decision device of the decision feedforward equalizer. The composite may be conveniently built up using a single decision device in the decision feedforward equalizer.

Inclusive and intensive performance analysis of electrical equalizers in a short-reach optical system using four-level pulse amplitude modulation (PAM-4) is presented in this paper. Two equalizers are used—a feedforward equalizer and decision feedback equalizer using the least mean square algorithm. The sensitivity to cut-off frequency for the transmitter and receiver filters, fiber length and number of equalizers taps in the means of the bit error rate vs. optical input power are shown. The analysis reveals the considerable impact of the filters’ bandwidth, particularly in the receiver, on the equalizer performance. These results and their reasons are analyzed and broadly discussed.

For serial wireline communication beyond 56 Gb/s, bandwidth-efficient modulation is needed. Four-level pulse amplitude modulation (4-PAM) has become the standard technique at 56–64 and 112 Gb/s. However, whereas decision feedback equalization (DFE) with 5 taps or more was common for 2-PAM links at lower data rates, the speculative look-ahead techniques required to satisfy a DFE's timing requirements at 56 Gb/s increase power consumption exponentially with the number of taps and the number of modulation levels. Thus, 4-PAM DFEs at 56 Gb/s are generally limited to 2 taps or fewer. This limitation, in turn, necessitates the use of long (10 taps or more) finite impulse response (FIR) feed-forward equalization (FFE) to accurately eliminate the intersymbol interference in long reach (LR) channels. Thus, LR receivers at 56–64 and 112 Gb/s comprise an analog-to-digital converter (ADC) followed by digital equalization, and the transmitters increasingly use a digital-to-analog converter (DAC) preceded by a digital filter. Discrete multitone (DMT) signalling obviates the need for a long FIR FFE and DFE, and has demonstrated better spectral efficiency than 4-PAM above 50 Gb/s. In this work, we consider the potential of DMT for wireline communication beyond 100 Gb/s. For example, a spectral efficiency of 2.5 bits/sample is achievable over an IEEE P802.3ck channel with 18 dB loss at 40 GHz, affording an aggregate data rate of 200 Gb/s at 80 GS/s with 150 fs of jitter and 1.26 mV of noise at the input to the receiver. Significant improvement in bit error rate (BER) is obtained by increasing DAC resolution to 8 bits.

Introduction Indoor infrared wireless systems using diuse channels are considered as the best form in respect of the network exibility. Infrared wireless system using ono keying code-division multiple-access (OOK-CDMA) has been proposed to realize multiple access in indoor infrared wireless communications, and the performance is analyzed on diuse channels [1]. It is shown in [1] that the bit error rate (BER) of indoor infrared wireless systems using OOK-CDMA on diuse channels is degraded excessively owing to the eects of ISI. To mitigate the eects of ISI, some equalization schemes for infrared wireless systems have been discussed [2]-[5]. The performance of the OOK-CDMA with the decision-feedback equalizer (DFE) and that of the OOK-CDMA with the decision-feedforward-andfeedback equalizer (DFFE) have been evaluated, and it is shown that the system with the DFFE has better performance than that of the system with the DFE [4]. The performance of the DS-CDMA with the feedfo

We present an adaptation scheme for a wireline-receiver equalizer composed of a feed-forward equalizer (FFE) and a decision-feedback equalizer (DFE), where the FFE is a cascaded connection of a high-frequency equalizer (HFEQ) and a low-frequency equalizer (LFEQ). The HFEQ is adjusted by using the conventional filter-pattern method. For the LFEQ adjustment, we used a modified filter-pattern method where the pattern matching is performed based on the mark ratio (i.e., the probability of `1'), to enhance the gain of the parameter-adjusting feedback loop. The adaptation is performed in the background, i.e., while data is being received.

We study the performance of feed-forward equalizers (FFEs) and decision-feedback equalizers (DFEs) in compensating chromatic dispersion and first-order polarization-mode dispersion (PMD) in optically amplified nonreturn-to-zero on-off keying (NRZ-OOK) and NRZ differential phase-shift-keying (DPSK) systems at 10 Gb/s. We use Monte Carlo simulation of the least-mean-square algorithm to estimate equalizer tap weights. Once stationary tap weights are obtained, we compute the bit-error ratio using an analytical method whose accuracy has been verified by simulation. We find that FFE and DFE offer the greatest improvement when combating first-order PMD with NRZ-OOK, reducing power penalties by about 45%. With NRZ-DPSK, the equalizers offer quite limited improvement.

As four‐level pulse‐amplitude‐modulation (PAM‐4) signal becomes widely adopted for high‐speed wireline communication, robust equalization is crucial due to reduced eye‐opening and increased sensitivity to channel loss, compared to PAM‐2. Utilizing analog‐to‐digital converters and digital signal processing with a feed‐forward equalizer (FFE) and a decision‐feedback equalizer (DFE), conventional equalizer adaptation may result in suboptimal bit‐error‐rate (BER) performance. This letter introduces an improved training algorithm to obtain the optimal equalizer configuration (i.e., main tap position in FFE and the DFE tap coefficient). The experimental results demonstrate superior BER performance of the proposed algorithm compared to the conventional approaches.

A decision-feedback equalizer (DFE) is the basis of a recent development of a quadruple diversity troposcatter modem which can operate up to a data rate of 12.6 Mbit/s in a 99% bandwidth of 15 MHz. In this paper a theoretical approach is developed for the calculation of average bit error rate (ABER), including the effects of intersymbol interference due to multipath and the finiteness of the transversal filters used to realize the DFE. By omitting the intersymbol interference effect, the calculation provides a lower bound which can be used to assess the intersymbol interference penalty for a particular DFE structure. The paper includes calculations of a DFE configuration which has a three tap forward filter with tap spacing equal to one-half a symbol interval. Measured performance results from fading channel simulator tests of a three tap forward filter DFE are presented for data rates from 1.5 to 12.6 Mbit/s and for a wide range of multipath statistical conditions. The results for this DFE configuration show (1) excellent agreement between calculated and measured ABER, (2) a small intersymbol interference penalty when the 2σ multipath spread is less than approximnately one-half the data symbol interval, and (3) successful operation at values of multipath spread up to twice the data symbol interval. In a sequel to this paper, the results of a field test of the DFE modem are presented. These live links test results are consistent with both the calculated and simulator measured data presented here.

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization