Accelerating Electromigration Wear-Out Effects Based on Configurable Sink-Structured Wires

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours 10^5X acceleration under the 150C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs.

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects in today's and future sub-10nm ICs, one critical issue is how to create stressing conditions so that the chip will fail exclusively under EM in a very short period of time so that EM signoff and validation can be carried out efficiently. In this work, we propose novel EM wearout-acceleration techniques for practical VLSI chips. We will first review the recently proposed three-phase physics-based EM models and discuss the important factors contributing to the EM aging process. Then we propose a new formula for fast estimation of the void's saturation volume for general multi-segment interconnect wires, which is important for EM mortality check. We then investigate two strategies to accelerate the EM failure process: reservoir-enhanced acceleration and temperature-based acceleration. First we show that multi-segment interconnects with reservoir structures and their stressing currents can be exploited to significantly speedup the EM wearout process. Such configurable reservoir-based wires are very flexible and can achieve various EM accelerations at the costs of some routing resources. Additionally, we show that further acceleration can be achieved by increasing temperature. On average, 10% increase in temperature yields about 10X wearout acceleration. However, purely temperature based acceleration is not possible since practical VLSI chips have temperature limitations which must be strictly enforced to ensure the chip only fails under EM, and not due to other reliability effects. In this study, we show that it is possible to achieve significantly high acceleration while staying within the feasible operating zones by combining the two acceleration techniques. Experimental results show that by combining temperature and reservoir accelerations, we can reduce the EM lifetime of a chip from 10 years down to a few hours (about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> acceleration) under the 150°C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs.

In this paper, an adaptive algorithm is proposed to perform electromigration (EM) assessment for full-chip power/ground networks. Based on the eigenfunction solutions, the proposed method improves the efficiency by properly selecting the eigenfunction terms and utilizing the closed-form eigenfunctions for commonly seen interconnect wires such as T-shaped or cross-shaped wires. It is demonstrated that the proposed method can trad-off well among the accuracy, efficiency and applicability of the eigenfunction based methods. The experimental results show that the proposed method is about three times faster than the finite difference method and other eigenfunction based methods.

In the power semiconductor industry, there is continuous development towards higher maximum current capability of devices while device dimensions shrink. This leads to an increase in current density which the devices have to handle, and raises the question if electromigration (EM) is a critical issue here. Generally, an EM failure can be described by the Black’s equation with temperature and current density as the main influencing factors. Normally, the current that the power packages need to handle lies in the range of 100 A. However, it should be noted that power devices exhibit asymmetric sizes of drain and source contacts. This may lead to higher current density at the source leads (area ratio drain/source: ~8x for QFN 5×6). Nevertheless, the source lead area is still much larger than that of the flip chip bumps (i.e., 28 times larger compared to a 100 μm micro-bump). This typically enhances the safety of the power device with respect to EM. However, with regard to future development towards higher maximum current capability, we intended to investigate further on the EM of power devices. In the present work, we focused on the PQFN 5×6 package to study the EM behavior of a power device soldered on a Printed Circuit Board (PCB). We employed the highest current (120 A) and temperature (150 °C) that the stress test system could handle to study EM in accelerated mode. First fails occurred after ~1200 h, which was much earlier than expected from previous flip-chip investigations. In addition, we found separation gaps in the solder joint between drain contact and PCB, which experienced the lowest current density in the whole test. Contradictorily, we observed only minor solder degradation at the source interface, regardless of the higher current density there. Nevertheless, the separating metal interfaces still correlated well with the current direction. Thermal simulations revealed that due to the self-heating of the device by the high current applied, both the drain and source leads were exposed to much higher temperatures (Tmax = 168 °C) than the PCB board which was kept under temperature control at 150 °C. This temperature difference resulted in a thermal gradient between the device and PCB which, in turn, triggered thermal migration (TM) in addition to EM. As TM for the drain contact occurred in the same direction as EM, it enhanced the degradation effect and therefore led to a shorter time-to-failure at the drain. In contrast to this, such an enhanced effect did not occur at the source side. As a result, we observed higher solder degradation at the drain side, which we did confirm by switching the current direction in the test. To minimize the TM effect, a special EM test vehicle, which used a Cu plate instead of the MOSFET chip, was designed and fabricated. Thermal simulation verified that the device operated at similar temperatures as the PCB board. Using this setup, it was possible to study EM in an accelerated mode and, thus, investigate the pure EM behavior of the power device.

This paper proposes a new power-ground (P/G) network sizing technique based on the recently proposed fast electromigration (EM) immortality check method for general multisegment interconnect wires and a new physics-based EM assessment technique for more accurate time to failure analysis. This paper first shows that the new P/G optimization problem, subject to the voltage IR drop and new EM constraints, can still be formulated as an efficient sequence of linear programing problem, where the optimization is carried out in two linear programing phases in each iteration. The new optimization will ensure that none of the wires fail if all the constraints are satisfied. However, requiring all the wires to be EM immortal can be overconstrained. To mitigate this problem, the first improvement is by means of adding reservoir branches to the mortal wires whose lifetime cannot be made immortal by wire sizing. This is a very effective approach as long as there is a sufficient reservoir area. The second improvement is to consider the aging effects of interconnect wires in the P/G networks. The idea is to allow some short-lifetime wires to fail and optimize the rest of the wires while considering the additional resistance caused by the failed wire segments. In this way, the resulting P/G networks can be optimized, such that the target lifetime of the whole P/G networks can be ensured and will become more robust and aging-aware over the expected lifetime of the chip. Numerical results on a number of IBM and self-generated power supply networks demonstrate that the new method can effectively reduce the area of the networks while ensuring immortality or enforcing target lifetime for all the wires, which is not the case for the existing current-density-constrained optimization methods.

The counterfeiting and recycled integrated circuits (ICs) has become a major security threat for commercial and military systems. In addition to the huge economic impacts, they post significant security and safety threats on those systems. In this paper, we propose a new lightweight on-chip aging sensor, which is based on the electromigration (EM)-induced aging effects for fast detection and prevention of recycled ICs. Our new EM-based aging sensor exploits the natural aging/failure mechanism of interconnect wires to time the aging of the chip. Compared with existing aging sensor, the new aging sensor can provide more accurate prediction of the chip usage time at smaller area footprints due to its simple structure. The new sensor is based on a newly proposed physics-based stress evolution model of EM effects for accurate prediction of the EM failure. As a result, we can design the interconnect wire structures based on copper interconnect technology so that the resulting wires will have detectable EM failure at a specific time with sufficient accuracy. In order to mitigate the problem of the inherent variations in the metal grain sizes and assess its impacts on the nucleation time of metal wires, a number of parallel properly structured wires are used in the sensor. The parameters of the wires are optimized using the new EM model. Our statistical and variational analysis shows that the proposed aging sensor can accurately predict the targeted failure times in the presence of both inherent uncertainties. Our study also shows that more parallel wires will lead to more accurate statistical predictions at costs of more areas.

Electromigration (EM) becomes one of the most challenging reliability issues for current and future ICs in 10-nm technology and below. In this article, a novel method is proposed for the EM hydrostatic stress analysis on 2-D multibranch interconnect trees, which is the foundation of the EM reliability assessment for large-scale on-chip interconnect networks, such as on-chip power grid networks. The proposed method, which is based on an eigenfunction technique, could efficiently calculate the hydrostatic stress evolution for multibranch interconnect trees stressed with different current densities and nonuniformly distributed thermal effects. The proposed method solves the partial differential equations of transient EM stress more efficiently since it does not require any discretization either spatially or temporally, which is in contrast to numerical methods, such as the finite difference method and finite element method. The accuracy of the proposed transient analysis approach is validated against the analytical solution and commercial tools. The convergence of the proposed method is demonstrated by numerical experiments on practical power/ground networks, showing that only a small number of eigenfunction terms are necessary for the accurate solution. Thanks to its analytical nature, the proposed method is also utilized in efficient EM analysis techniques, such as searching for the void nucleation time by a modified bisection algorithm. The numerical results show that the proposed method is 10X–100X faster than the finite difference method and scales better for larger interconnect trees.

A series of electromigration (EM) experiments were undertaken to evaluate the time to failure performance of solder joints comprised of Sn-Ag and Sn-Cu alloys in combination with three solderable surface finishes, Cu, Ni-Au and Ni-Cu. The opposing pad structure in the solder joints was the same in all experiments and was comprised of a layered structure, simulating Ni based under - bump - metallurgies (UBM) for controlled collapse chip connection (C4). As anticipated the Sn grain size was large with the typical solder joint containing only a few grains. In all experiments, reported here, the electron current exited the pad with the surface finish under evaluation and passed into the solder. Two failure modes were identified. The manifested failure mode depended on the orientation of the c-axis of the larger Sn grains in the solder joint with respect to the applied current direction. When the c-axis is not closely aligned with the current direction, cavitation at solder-IMC interface leads to electrical failure. A more rapid failure mode occurred when the c-axis was closely aligned with the current direction. With this alignment the interfacial IMC structures were swept away by rapid diffusive processes from the pad surface and the pad material was quickly consumed. Interfacial void formation leads to rapid failure in this mode. The Sn-Ag solder appeared to demonstrate greater microstructural stability. But, clearly the best EM performance was seen with the addition of significant levels of Cu to the Sn-Ag alloy. This alloy modification showed the best EM lifetime in combination with a Ni pad structure.

Electromigration (EM) is a traditional reliability concern, aggravated recently due to intense shrinking of wire sizes and the increase in the number of interconnections on a system-on-chip (SoC). Thereby, it challenges the state-of-the-art in design, physics, process and CAD processes. To that regard, we propose a new EM check method named Via Node Vector method. The conventional EM check ignores the lead EM interaction in circuits and only checks the local current densities. The new method addresses the EM interactions and checks the EM reliability at the lead connection sites (called via node). It converts the electrical current density of each lead into an effective current density for the EM interaction consideration. For this, we introduce three new factors: length (FL), width (FW), and interaction (FB). The effective current density divergence at a via node is derived as an addition of the effective current densities of all the interacting leads, which is a close proxy to represent the physical atomic flux divergence at the via node. This divergence at a via node can then be readily compared with the technology EM spec. The proposed method is successfully applied to 28nm node IPs and shows up to ~4X higher safe operating frequency than the conventional method allows. Additionally, it successfully identifies risky sites missed by conventional check. The Via Node Vector Method will provide higher performance with reliability in designing advanced digital and analog circuits.

Electromigration (EM) is a major concern for very large-scale integration (VLSI) interconnect reliability, particularly for interconnect trees with multibranch metal wires representing continuously connected metal (Cu) lines terminated at diffusion barriers. For EM modeling and assessment, one important problem is to perform fast EM time to failure analysis for practical VLSI chips. Compact modeling for EM effects for the interconnect tree has been studied recently to better EM signoff analysis. But the existing method cannot consider wires stressed under time-varying temperature, which is very typical for practical chip working conditions. In this paper, we develop the exact analytic model for the stress evolution of interconnect trees under different current density and varying segment length from the first principle. Due to the difficulty in obtaining the exact analytical solution, we focus on three-terminal wire in this paper. The stress evolution is modeled by two Korhonen’s equations coupled through boundary conditions which are solved with the Laplace transformation technique. The new analytical EM model is further extended to consider the time-varying temperature stressing condition and initial non-zero residual stress. The proposed method is compared with the finite-element method (FEM) tool COMSOL, the recently proposed eigenfunction-based method, and the published EM simulator XSim. The comparison shows that the analytical solution agrees well with the results from the FEM numerical analysis. It uses much fewer terms compared to the eigenfunction method for the same accuracy. It also agrees very well with XSim, which is consistent with the previously reported measured results.

Electromigration (EM) is considered to be one of the most important reliability issues for current and future ICs in 10nm technology and below. In this paper we focus on the EM stress evaluation for one-dimensional multi-segment interconnect wires in which all the segments have the same direction, which is a common routing structure for power grid networks. The proposed method, which is based on integral transform technique, could efficiently calculate the hydrostatic stress evolution for multi-segment metal wires stressed with different current densities. The new method can also naturally consider the pre-existing residual stresses coming from thermal or other stress sources. Based on this new transient EM assessment method, a full-chip assessment algorithm for power grid networks is then proposed. The new algorithm is also based on the IR-drop metrics for failure assessment of the power grid networks. However, it finds the precise location and time of EM-induced void nucleation by directly checking the time-changing hydrostatic stresses of all the wires. The resulting EM assessment method can ensure sufficient accuracy of the EM verification for large scale power grid networks without sacrificing the efficiency. The accuracy of the proposed transient analysis approach is validated against the numerical analysis. Also the resulting EM-aware full-chip power grid reliability analysis has been demonstrated and compared with existing methods.

Electromigration (EM) in VLSI chips has become a major reliability issues in nanometer VLSI design. Traditional compact EM models cannot give accurate predictions about the stress evolution over all stress conditions for complicated multi-branch interconnect structures. In this paper, we try to mitigate this problem by performing finite difference method (FDM) for the EM effects in multi-branch interconnects based on the kinetics of the first principle of EM physics. We start with the partial differential equations that describe the fundamental hydrostatic stress evolution for both the void nucleation and void growth phases with proper boundary and initial conditions for typical multi-branch metal wires: the single 2-terminal wire, and the straight-line 3-terminal wires. The new FDM for EM analysis approach can easily accommodate existing non-uniformly distributed residual stress, while existing compact EM models cannot. Time varying temperature and current, which are also difficult to model with existing methods, can also be considered with this method. Numerical results show that the proposed FDM EM analysis method agrees with the COMSOL based finite element method in terms of accuracy.

Electromigration-induced microstructure evolution and failure mechanism of sintered nano-Ag joint

An improved and efficient method for static estimation of average and root-mean-squared currents used for electromigration (EM) reliability analysis is presented in this work. Significantly different from state-of-the-art, the proposed method gives closed-form expressions for average and RMS currents in one complete cycle. The proposed method can be readily configured to work with different combinations of ramp and exponential waveforms. Subsequently, the inadequacies of using conventional EM-severity metrics: either the net's lumped capacitance or the net's effective capacitance, along with the regular timing slew, for EM analysis are outlined. As a correction, and, application of proposed method, we provide formulations for deriving the effective “EM” slew, which can be used with conventional approaches to accurately compute the currents. Further, unlike traditional wisdom, we note that not just the RMS current, but even the total charge transfer can depend on the waveform type, and propose formulations to that regard. Additionally, for the first time, we present a method for incorporating the driver's dynamic IR drop while computing RMS currents. Alongside, we lay recommendations for ensuring the standard-cell EM safety at chip level. Finally, we share model-validation results from a production 40 nm design, enabling a 40% higher performance closure.

Intermetallic compounds (IMCs) growth is often accompanied by void and crack formation. It can reduce the mechanical properties and reliability of solder joints. In this paper, based on the Cu mass transport mechanisms, a theory model is established to analyze the IMC growth behaviors on Cu/Sn/Cu interconnection structures. The influence of IMC dissolution process is considered to investigate the polarity effect of electromigration (EM) on kinetics of IMC growth. Verified by reported experimental data, the model can accurately calculate the thickness of IMC growth under specific temperature and current stressing. The model reveals that during thermal aging, the thickness growth of IMC on Cu–Sn interfaces has a parabolic curve relationship with time. While under current stressing, EM Cu flux in Sn solder accelerates the anode’s IMC growth and motivates the transition of its thickness growth from parabola-like curves to a linear-like relationship. The cathode’s IMC will reach constant thickness with stressing time, which can be primarily determined by the dynamic equilibrium between Cu dissolution flux and chemical Cu flux. When the initial thickness of IMC is larger than this constant, the IMC on the cathode side follows a parabola-like curve to dissolve. Otherwise, it follows a parabola-like curve to increase.