EM-Aware and Lifetime-Constrained Optimization for Multisegment Power Grid Networks

In this work, we propose a novel electromigration (EM) wear-out acceleration technique for fast EM reliability-testing and aging-analysis of practical VLSI chips. The new acceleration technique is based on the observation that sink structures have a significant impact on the lifetime of multisegment interconnect wires. We develop a new configurable sink-structured interconnect wire in which the current in the sink segment can be activated/deactivated dynamically during operation. Using this method, we show how an interconnect structure, which is initially immortal to EM effects, can be induced to fail very quickly. Furthermore, we use a robust failure scheme which considers both early and late failures depending on the wire topology and current direction. The most significant contribution of the proposed work is that it enables EM accelerated testing at low temperature and voltage. This feature enables the testing of EM wear-out in isolation without invoking other reliability effects which are also accelerated by the traditional stressing conditions. Using the proposed method, we can achieve a lifetime reduction from 10+ years to a few days, or even hours, at relatively low temperatures, which is very desirable for practical EM testing of typical nanometer CMOS ICs.

The counterfeiting and recycled integrated circuits (ICs) has become a major security threat for commercial and military systems. In addition to the huge economic impacts, they post significant security and safety threats on those systems. In this paper, we propose a new lightweight on-chip aging sensor, which is based on the electromigration (EM)-induced aging effects for fast detection and prevention of recycled ICs. Our new EM-based aging sensor exploits the natural aging/failure mechanism of interconnect wires to time the aging of the chip. Compared with existing aging sensor, the new aging sensor can provide more accurate prediction of the chip usage time at smaller area footprints due to its simple structure. The new sensor is based on a newly proposed physics-based stress evolution model of EM effects for accurate prediction of the EM failure. As a result, we can design the interconnect wire structures based on copper interconnect technology so that the resulting wires will have detectable EM failure at a specific time with sufficient accuracy. In order to mitigate the problem of the inherent variations in the metal grain sizes and assess its impacts on the nucleation time of metal wires, a number of parallel properly structured wires are used in the sensor. The parameters of the wires are optimized using the new EM model. Our statistical and variational analysis shows that the proposed aging sensor can accurately predict the targeted failure times in the presence of both inherent uncertainties. Our study also shows that more parallel wires will lead to more accurate statistical predictions at costs of more areas.

As technology scales down to nanometres it severely affects the IR (Voltage) drop. Although checking this problem in the earlier stages can speed up the analysis, not many tools are available to fix this. Recently Redhawk has included a new feature to fix the electromigration (EM) and IR voltage drop and achieve signoff. It significantly reduces the manual effort required to minimize the electromigration and IR (EMIR). In this paper, a double data rate (DDR) memory block is implemented using 14 nm technology, the EM and IR voltage drop are analysed. The proposed design has reduced the IR voltage drop values to less than 2% of the VDD value (0.99 V), and concerning EM variation could converge to around 83%. Typically, the value of the EM violations should be less than 100%. Hotspot reduction has been done by adding the metal strips. Thus, it can be concluded that by adding metal strips, and by providing a stronger power delivery network (PDN), we can mitigate the hotspots and therefore reduce the IR voltage drop and EM violations. The worst violated path in the static run before clearing violations is in the Metal (M1) layer has a value of 28.50 mV, and EM violating path is 192%. The total power consumption is found to be 4.11 W before clearing the static EMIR run violations. The worst violating path for the static run after clearing violations is in the M1 layer has a value of 5.60 mV. The total power consumption is measured to be 1.4 W for the static run after clearing violations and, EM violating path is put down to 83%. After using power grid augmentation (PGA), the total power consumption is reduced to 1.29 W. Therefore, there is an IR voltage drop of 28.5mV before PGA and 5.6mV after PGA. From the existing methodology (double row optimization) we can see an IR voltage drop of 29mV as the worst instance drop.

<div class="section abstract"> <div class="htmlview paragraph">The scope of this report is to capture fundamental principles of selecting a wire size for an aerospace application using the method prescribed in the AS50881 standard and additional calculations, not found in AS50881, to ensure the wire selection will adequately perform in the specific physical and environment conditions.</div> <div class="htmlview paragraph">This report covers wire selection and sizing as part of the electrical wire interconnection systems (EWIS) used in aerospace vehicles. Aerospace vehicles include manned and unmanned airplanes, helicopters, lighter-than-air vehicles, missiles, and external pods. This document does not apply to wiring inside of airborne electronic equipment but shall apply to wiring externally attached to such equipment.</div> <div class="htmlview paragraph">Wire selection must consider physical and environmental factors to size wires such that they have sufficient mechanical strength, do not exceed allowable voltage drop levels, are protected by materials or circuit protection devices, and meet circuit current carrying requirements. For electrical power feeders and distribution, or EWIS applications, other information and environmental and installation limitations are also needed to adequately evaluate and select the correct wire size for a specific application and meet design requirements.</div> <div class="htmlview paragraph">The report presents only fundamental principles and guidelines and cannot adequately cover all aspects and complexities associated with wire selection and sizing. Some of the calculations in this report have been simplified to demonstrate the process for validating a wire size selection for a design application. More precise calculations should be investigated and evaluated to ensure proper assessment of each individual calculation in this report.</div></div>

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects in today's and future sub-10nm ICs, one critical issue is how to create stressing conditions so that the chip will fail exclusively under EM in a very short period of time so that EM signoff and validation can be carried out efficiently. In this work, we propose novel EM wearout-acceleration techniques for practical VLSI chips. We will first review the recently proposed three-phase physics-based EM models and discuss the important factors contributing to the EM aging process. Then we propose a new formula for fast estimation of the void's saturation volume for general multi-segment interconnect wires, which is important for EM mortality check. We then investigate two strategies to accelerate the EM failure process: reservoir-enhanced acceleration and temperature-based acceleration. First we show that multi-segment interconnects with reservoir structures and their stressing currents can be exploited to significantly speedup the EM wearout process. Such configurable reservoir-based wires are very flexible and can achieve various EM accelerations at the costs of some routing resources. Additionally, we show that further acceleration can be achieved by increasing temperature. On average, 10% increase in temperature yields about 10X wearout acceleration. However, purely temperature based acceleration is not possible since practical VLSI chips have temperature limitations which must be strictly enforced to ensure the chip only fails under EM, and not due to other reliability effects. In this study, we show that it is possible to achieve significantly high acceleration while staying within the feasible operating zones by combining the two acceleration techniques. Experimental results show that by combining temperature and reservoir accelerations, we can reduce the EM lifetime of a chip from 10 years down to a few hours (about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> acceleration) under the 150°C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs.

In this paper, an adaptive algorithm is proposed to perform electromigration (EM) assessment for full-chip power/ground networks. Based on the eigenfunction solutions, the proposed method improves the efficiency by properly selecting the eigenfunction terms and utilizing the closed-form eigenfunctions for commonly seen interconnect wires such as T-shaped or cross-shaped wires. It is demonstrated that the proposed method can trad-off well among the accuracy, efficiency and applicability of the eigenfunction based methods. The experimental results show that the proposed method is about three times faster than the finite difference method and other eigenfunction based methods.

The subject matter of the article is information processing in the production and consumption of infocommunication services in multiservice networks. The goal of the study is to investigate the process of information processing in multiservice networks and to identify the quality class management tasks of infocommunication services production and consumption could be connected by methods of the several variable functions unconditional optimization. The tasks to be solved are: to analyze the processes of production and use of infocommunication technologies, taking into account the possibility of their optimization according to the QoS procedure; to propose a formulation of the QoS procedure optimization problem in a form suitable for solving by unconstrained optimization methods; to investigate the unconditional optimization application possibility of the methods according to the QoS procedure in the production and consumption of infocommunication services. General scientific and special methods of scientific knowledge are used. The following results were obtained: On the basis of the analysis of production processes and use of information communication services in different segments of the service market the possibilities of infocommunication services optimizing for QoS procedures were identified. The problem of optimization in multiservice networks providing QoS to be formulated as a problem of unconditional optimization of the two variables function. The possibility of applied use of methods of crazy optimization of QoS procedure is shown on the application of integral business model of convergent production and implementation of information communication services. Conclusions. The production and use of infocommunication services today is convergent. The definition of a single variable for the coordination of processes in the entire chain of production and consumption of infocommunication services on a unified criterion will support QoS convergent production and implementation of infocommunication services. Really, the analytical method is practically not implemented in multiservice networks, as it is difficult to approximate the second derivative. If a simple approximation of the first derivative is possible, use gradient methods. The simplest to implement method is considered to be the method of fragmentation of the step. The definition of optimization paths by the QoS procedure will provide in the multiservice networks in the field of state regulation the necessary reliability, security and efficiency, in particular by optimizing the time of packets.

The crosstalk noise induced on a net depends on its wire size, its driver size and the sizes of the aggressor gates driving its coupled nets. The problem of crosstalk noise optimization at post-route level is difficult due to the cyclic dependency on aggressor and victim driver sizes, resulting in a conflicting situation. Game theory provides a natural framework for handling conflicting objectives and allows simultaneous optimization of multiple parameters. The formulation of a convex objective function is a requirement in order to obtain better optimization in a game theoretic framework. This property is exploited to solve the cyclic dependency of crosstalk noise on its gate and wire sizes, while modeling the problem of simultaneous optimization of interconnect delay and crosstalk noise. A game is modeled with the crosstalk noise and interconnect delay of the chosen net as the players, the possible gate and wire sizes as the strategy set and the analytical expressions for crosstalk noise and interconnect delay as their respective expected payoffs. The time and space complexity of the proposed integrated sizing algorithm is linear in terms of the number of gates and wires in the design. Experimental results on several medium and large open core designs indicate average improvements of 27.52% and 34.03% for interconnect delay and crosstalk noise respectively, achieved by game theoretic gate sizing based on noise criticality over and above the optimization from the Cadence place and route tools without any area overhead or the need for rerouting

Solving optimization problems with sparse or low-rank optimal solutions has been an important topic since the recent emergence of compressed sensing and its matrix extensions such as the matrix rank minimization and robust principal component analysis problems. Compressed sensing enables one to recover a signal or image with fewer observations than the “length” of the signal or image, and thus provides potential breakthroughs in applications where data acquisition is costly. However, the potential impact of compressed sensing cannot be realized without efficient optimization algorithms that can handle extremely large-scale and dense data from real applications. Although the convex relaxations of these problems can be reformulated as either linear programming, second-order cone programming or semidefinite programming problems, the standard methods for solving these relaxations are not applicable because the problems are usually of huge size and contain dense data. In this dissertation, we give efficient algorithms for solving these “sparse” optimization problems and analyze the convergence and iteration complexity properties of these algorithms. Chapter 2 presents algorithms for solving the linearly constrained matrix rank minimization problem. The tightest convex relaxation of this problem is the linearly constrained nuclear norm minimization. Although the latter can be cast and solved as a semidefinite programming problem, such an approach is computationally expensive when the matrices are large. In Chapter 2, we propose fixed-point and Bregman iterative algorithms for solving the nuclear norm minimization problem and prove convergence of the first of these algorithms. By using a homotopy approach together with an approximate singular value decomposition procedure, we get a very fast, robust and powerful algorithm, which we call FPCA (Fixed Point Continuation with Approximate SVD), that can solve very large matrix rank minimization problems. Our numerical results on randomly generated and real matrix completion problems demonstrate that this algorithm is much faster and provides much better recoverability than semidefinite programming solvers such as SDPT3. For example, our algorithm can recover 1000 × 1000 matrices of rank 50 with a relative error of 10−5 in about 3 minutes by sampling only 20 percent of the elements. We know of no other method that achieves as good recoverability. Numerical experiments on online recommendation, DNA microarray data set and image inpainting problems demonstrate the effectiveness of our algorithms. In Chapter 3, we study the convergence/recoverability properties of the fixed-point continuation algorithm and its variants for matrix rank minimization. Heuristics for determining the rank of the matrix when its true rank is not known are also proposed. Some of these algorithms are closely related to greedy algorithms in compressed sensing. Numerical results for these algorithms for solving linearly constrained matrix rank minimization problems are reported. Chapters 4 and 5 considers alternating direction type methods for solving composite convex optimization problems. We present in Chapter 4 alternating linearization algorithms that are based on an alternating direction augmented Lagrangian approach for minimizing the sum of two convex functions. Our basic methods require at most O(1/e) iterations to obtain an e-optimal solution, while our accelerated (i.e., fast) versions require at most O(1/ 3 ) iterations, with little change in the computational effort required at each iteration. For more general problem, i.e., minimizing the sum of K convex functions, we propose multiple-splitting algorithms for solving them. We propose both basic and accelerated algorithms with O(1/e) and O(1/ 3 ) iteration complexity bounds for obtaining an e-optimal solution. To the best of our knowledge, the complexity results presented in these two chapters are the first ones of this type that have been given for splitting and alternating direction type methods. Numerical results on various applications in sparse and low-rank optimization, including compressed sensing, matrix completion, image deblurring, robust principal component analysis, are reported to demonstrate the efficiency of our methods.

Contributors

Quantum variational optimization has been posed as an alternative to solve optimization problems faster and at a larger scale than what classical methods allow. In this paper we study systematically the role of entanglement, the structure of the variational quantum circuit, and the structure of the optimization problem, in the success and efficiency of these algorithms. For this purpose, our study focuses on the variational quantum eigensolver (VQE) algorithm, as applied to quadratic unconstrained binary optimization (QUBO) problems on random graphs with tunable density. Our numerical results indicate an advantage in adapting the distribution of entangling gates to the problem's topology, specially for problems defined on low-dimensional graphs. Furthermore, we find evidence that applying conditional value at risk type cost functions improves the optimization, increasing the probability of overlap with the optimal solutions. However, these techniques also improve the performance of Ans\"atze based on product states (no entanglement), suggesting that a new classical optimization method based on these could outperform existing NISQ architectures in certain regimes. Finally, our study also reveals a correlation between the hardness of a problem and the Hamming distance between the ground- and first-excited state, an idea that can be used to engineer benchmarks and understand the performance bottlenecks of optimization methods.

This study deals with the particle swarm optimization approach for optimal power dissipation in VLSI interconnect driven routing technique. Interconnect power dissipation is a major challenging research problem in Deep Submicron (DSM) regime that affects the overall circuit performance. The Buffer Insertion Buffer Sizing and Wire Sizing (BISWS) is considered for minimizing the power dissipation in VLSI circuits using interconnect wires. The shortest path constraints, buffer insert constraints and wire size constraints are used to analysis the power consumption considered for analysis. The closed form expressions for optimal power allocation is also derived. These expressions can be used to estimate the power dissipation efficiently in the physical design stages of the VLSI. It is observed that the power dissipation is optimal using the shortest path between source to sink. A novel optimization algorithm is introduced to model delay and bandwidth analytically derived and analyzed. The proposed optimization algorithm is analyzed and compared for 65, 45 and 32 nm CMOS technologies.

This paper establishes a framework for solving some optimization problems with linear constraints using simplex-type methods. The problems include those found in linear programs, linear fractional programs, and generalized linear fractional programs. In this study, these problems refer to a standard form of minimizing a single parameter subject to parameterized linear equations. Based on the analysis of parameterized basis-based solutions, a unified simplex-type approach is proposed. The adaptability of the parameterized model and that of the solution procedure are discussed. In particular, the proposed algorithm can prevent cycling when compared with the conventional simplex method used for solving linear programs.

Electromigration (EM) in VLSI chips has become a major reliability issues in nanometer VLSI design. Traditional compact EM models cannot give accurate predictions about the stress evolution over all stress conditions for complicated multi-branch interconnect structures. In this paper, we try to mitigate this problem by performing finite difference method (FDM) for the EM effects in multi-branch interconnects based on the kinetics of the first principle of EM physics. We start with the partial differential equations that describe the fundamental hydrostatic stress evolution for both the void nucleation and void growth phases with proper boundary and initial conditions for typical multi-branch metal wires: the single 2-terminal wire, and the straight-line 3-terminal wires. The new FDM for EM analysis approach can easily accommodate existing non-uniformly distributed residual stress, while existing compact EM models cannot. Time varying temperature and current, which are also difficult to model with existing methods, can also be considered with this method. Numerical results show that the proposed FDM EM analysis method agrees with the COMSOL based finite element method in terms of accuracy.

Electromigration (EM) is a traditional reliability concern, aggravated recently due to intense shrinking of wire sizes and the increase in the number of interconnections on a system-on-chip (SoC). Thereby, it challenges the state-of-the-art in design, physics, process and CAD processes. To that regard, we propose a new EM check method named Via Node Vector method. The conventional EM check ignores the lead EM interaction in circuits and only checks the local current densities. The new method addresses the EM interactions and checks the EM reliability at the lead connection sites (called via node). It converts the electrical current density of each lead into an effective current density for the EM interaction consideration. For this, we introduce three new factors: length (FL), width (FW), and interaction (FB). The effective current density divergence at a via node is derived as an addition of the effective current densities of all the interacting leads, which is a close proxy to represent the physical atomic flux divergence at the via node. This divergence at a via node can then be readily compared with the technology EM spec. The proposed method is successfully applied to 28nm node IPs and shows up to ~4X higher safe operating frequency than the conventional method allows. Additionally, it successfully identifies risky sites missed by conventional check. The Via Node Vector Method will provide higher performance with reliability in designing advanced digital and analog circuits.