Electromigration and IR Voltage Drop Reduction Technique on DDR Memory Block Using Power Grid Augmentation

In the past year, AMOLED have been widely used in smartphones, laptops, and vehicles. Local excitation luminance is one of the important parameters to measure AMOLED quality. This feature is of great significance for realization of HDR video and getting better visual experience in sunlight environment. Due to IR drop effect in the local display, the performance of peak luminance is often skewed by luminance, chrominance, and gamma curves. The solution is adding a set of Gamma curve debugging at peak luminance of local display, which results in longer take time (TT) and greater aging pressure at high luminance. In this paper, we propose a novel peak luminance correction method based on Global IR (GIR) voltage drop compensation system. In the compensation system, GIR compensation Look‐Up Tables (LUT) is used to accurately tune the luminance, chrominance, and gamma curves that correspond to the local excitation luminance.

With increasing core counts ushering in power-constrained 3-D multiprocessor system-on-chips (MPSoCs), optimizing communication power dissipated by the 3-D network-on-chip (NoC) fabric is critical. At the same time, with increased power densities in 3-D ICs, problems of IR drops in the power delivery network (PDN) as well as thermal hot spots on the 3-D die are becoming very severe. Even though the PDN and NoC design goals are nonoverlapping, both the optimizations are interdependent. Unfortunately, designers today seldom consider the design of the PDN, while designing NoCs. Moreover, for each new configuration of computation core and communication mapping on an MPSoC, the corresponding intercore communication patterns, 3-D on-chip thermal profile, as well as IR-drop distribution in the PDN can vary significantly. Based on this observation, we propose a novel design-time system-level application-specific cosynthesis framework that intelligently maps computation and communication resources on a die, for a given workload. The goal is to minimize the NoC power as well as chip-cooling power and optimize the 3-D PDN architecture; while meeting performance goals and satisfying thermal constraints, for a microfluidic cooling-based application-specific 3-D MPSoC. Our experimental results indicate that the proposed 3-D NoC-PDN cosynthesis framework is not only able to meet PDN design goals unlike prior 3-D NoC synthesis approaches, but also provides better overall optimality with the solution quality improvement of up to 35.4% over a probabilistic metaheuristic-based cooptimization approach proposed in prior work.

Power integrity design has been a challenging task especially with devices that high in power consumption but require high performance and with very tight voltage budgeting. Most of the time, the solution space is also limited by the product cost target. Designer will need to validate the power delivery network (PDN) performance with various design operation activities to identify the worst-case current profile. Step load current is one of the common profiles that is used to verify the PDN dynamic noise against the voltage specification. This paper introduces a formulation to estimate the PDN transient response to the step load current profile and the induced 1st droop voltage noise. It provides a quantitative model to analyze the PDN characteristic and its response with different step load bandwidth profile. PDN bandwidth metric is also introduced in the formulation to study the relationship with the step load bandwidth. The PDN step load response will be separated to resistive and reactive impedance response and as well the ripple from the LC oscillation. This serves as the dynamic voltage budgeting methodology with respect to 1st droop event to quantify the IR drop and ripple voltage noise budget across board, package and die to meet the product voltage specification.

This paper presents a novel approach and techniques for electromigration (EM) assessment in power delivery networks. An increase in the voltage drop above the threshold level, caused by EM-induced increase in resistances of the individual interconnect segments, is considered as a failure criterion. This criterion replaces a currently employed conservative weakest segment criterion, which does not account an essential redundancy for current propagation existing in the power-ground (p/g) networks. EM-induced increase in the resistance of the individual grid segments is described in the approximation of the physics-based formalism for void nucleation and growth. A developed technique for calculating the hydrostatic stress distribution inside a multi branch interconnect tree allows to avoid over optimistic prediction of the time to failure made with the Blech-Black analysis of individual branches of interconnect segment. Experimental results obtained on the IBM benchmark circuit validate the proposed methods.

In modern integrated circuits, the Electromigration (EM) effects are not just seen on power delivery networks. EM is also an increasing problem in the internal metal wires of cells, referred as cell-internal signal Electromigration. In this work we present a detailed analysis of the cell-internal signal Electromigration effects considering different logic gates. The lifetime optimization by placing the output pin of the gates is dependent of the output wire shape and the logic of the gate. We are also presenting ways to improve the lifetime of the cells optimizing the cell layout.

This paper presents a hybrid modelling approach that combines physics-based electromigration modelling (PEM) and statistical methods to evaluate the electromigration (EM) limits of nano-interconnects in mesh networks. The approach, which is also compatible with standard Place and Route (P&R) tools and practises, takes into account the positive impact of network redundancy on EM current limits. The numerical simulations conducted in this study show that conventional methods underestimate the EM current limits of a power delivery network (PDN) unit-cell by 80% due to their lack of consideration for redundancy. Additionally, the time-to-failure (TTF) distributions of a PDN unit-cell obtained by the developed modelling framework adhered to a lognormal distribution, where the lognormal sigma, σlogn, exhibits a 55% reduction compared to that of the single constituent interconnects. The study also found the negative voltage (i.e., ground or Vss) grid to be more susceptible to EM than the positive voltage, i.e., Vdd grid. In the examined grid unit-cell design, both the number of interconnect sites prone to voiding and also the magnitude of the peak tensile stress within the nano-interconnects were found to be two times as high in the Vss case compared to Vdd. The lognormal sigma of TFF for the grid unit-cells, σlogn-tile, show a marked reduction compared to the lognormal sigma of the constituent single interconnects, σlogn, with a 50% and 66% decrease compared to single interconnects, for downstream (Vss) and upstream (Vdd), respectively. In addition, σlogn-tile was three times higher for downstream (Vss) compared to upstream (Vdd), whilst, in contrast, this difference was only 2-fold at the single interconnect level. TTF50% was predicted to be 4.13-fold higher at the grid unit-cell level for the upstream compared to downstream operation, which was also more pronounced than in the single interconnect level where the difference was only 2-fold. This research provides valuable insights into the EM ageing of nano-interconnects in mesh networks and could pragmatically enhance the accuracy of EM compliance evaluation methods.

Voltage drop (IR drop) and Electromigration (EM) reliability are two key related aspects for on-chip power grid design considerations. Good EM reliability ensures no EM induced void formation in the interconnect to cause a fatal resistance increase during product lifetime. It is important to understand the difference of EM characteristics between a power grid and traditional single link EM structures. In this paper, we report the experimental results of EM characteristics of power grid like structures, to demonstrate the power grid design environment, and physical and statistical redundancy benefits for EM reliability. These results can serve as fundamental references for power grid EM limit determination.

This paper introduces a process that allows customers to do IRDrop analysis on the package/SiP and PCB level. The component information such as the package model, power consumption and voltage regulator module (VRM) as well as power delivery network circuit can be used at the package and board level to perform static IRDrop analysis. The power consumption is used to obtain the current excitation while the VRM pins are used to provide the power supply. For the complicated package and PCB geometry structure, the progressive mesh scheme is used to extract the DC circuit model for their power delivery network. In order to meet the tolerance of current and voltage drop, the required VRM and IC components locations as well as stackup can be optimized according to the voltage drop in DC domain. The user can also view the voltage drop, current and temperature rise.

In emerging 3D NoC-based chip multiprocessors (CMPs), aging in circuits due to bias temperature instability (BTI) stress is expected to cause gate-delay degradation that, if left unchecked, can lead to untimely failure. Simultaneously, the effects of electromigration (EM) induced aging in the on-chip wires, especially those in the 3D power delivery network (PDN), are expected to notably reduce chip lifetime. A commonly proposed solution to mitigate circuit-slowdown due to aging is to hike the supply voltage; however, this increases current-densities in the PDN due to the increased power consumption on the die, which in turn expedites PDN-aging. We thus note that mechanisms to enhance lifetime reliability in 3D NoC-based CMPs must consider circuit-aging together with PDN-aging. In this paper, we propose a novel runtime framework (ARTEMIS) for intelligent dynamic application-mapping and voltage-scaling to simultaneously manage aging in circuits and the PDN, and enhance the performance and lifetime of 3D NoC-based CMPs. We also propose an aging-enabled routing algorithm that balances the degree of aging between NoC routers and cores, thereby increasing the combined lifetime of both. Our framework also considers dark-silicon power constraints that are becoming a major design challenge in scaled technologies, particularly for 3D stacked CMPs. Our experimental results indicate that ARTEMIS enables the execution of 25 percent more applications over the chip lifetime compared to state-of-the-art prior work.

Power supply induced clock jitter accumulation is a function of several variables including the power supply rejection characteristics of circuits in the signal path, signal path electrical length, signaling frequency, and voltage supply noise magnitude and frequency. Brute force, closed-loop, transistor-level modeling and simulation of clock timing in the presence of an extracted power delivery network are resource intensive. In addition, circuit and power delivery network designs are often not complete enough to run such analyses at an early stage in the design cycle, and the longer a design waits to identify circuit and supply sensitivities, the more costly the corrections become. Understanding the relationships between the signal path electrical length, signaling frequency and supply noise frequency enables early jitter estimation and can be used to drive both circuit and power delivery network design optimization. This paper summarizes the general inter-dependencies between these variables and then demonstrates how these principles might be used to make design optimizations in the context of the Low Power Double Data Rate Four (LPDDR4) interface.

The high current densities carried by the interconnects have a direct impact on the back-end-of-line (BEOL) reliability degradation as they locally increase the temperature by Joule heating, and they lead to drift in the metal atoms. Local increase in temperature due to Joule heating will lead to thermal gradients along the interconnects inducing degradation through thermomigration. As the power density of the chip increases, thermal gradients may become a major reliability concern for scaled Cu interconnects. Therefore, it is of utmost relevance to fundamentally understand the impact of thermal gradients in metal migration. Our studies show that by using a combined modelling approach and a dedicated test structure we can assess the local temperatures and temperature gradients profiles. Moreover, with long-term experiments, we are able to successfully generate voids at the location of highest temperature gradients. Additionally, the main consequence of scaling the Cu interconnects is the dramatic drop of EM lifetime (Jmax). Currently the experimentally obtained EM parameters are used at system design level to set the current limits through the interconnect networks. However, this approach is very simplistic and neglects the benefits provided by the redundancy and interconnectivity from the network. Our studies by using a system-level physics-based EM simulation framework which can determine the EM induced IR drop at the standard cell level, show that the circuit reliability margins of the power delivery network (PDN) can be further relaxed.

Highly reliable technology and design are vital to the future of the semiconductor industry for three reasons namely, technology scaling, new materials and new workload. Firstly, geometry scaling of technology has exacerbated multiple reliability phenomena, and managing the reliability of these devices itself has limited performance and target design metrics. For example, interconnects are heavily resistive today at sub-7nm nodes, serving as a key bottleneck in high-performance designs. One of the main reasons is that the copper wires require thick barrier-liners that consume useful conductor area to maintain wire reliability. Worsening back-end-of-the-line electromigration (EM) at advanced nodes also forces designers to limit high-performance gates in design, therefore limiting the peak design performance. Secondly, the rapid increase in the number of new materials introduced to further Moore’s law scaling has exposed designers to work with devices of little or unknown reliability, potentially leading to too much pessimism in guard-banding while designing for these new devices. Understanding the underlying failure mechanisms and quantifying their impact is key to determining the right design practices. The introduction of new wire materials like Cobalt/Ruthenium after almost two decades of copper wires is one such example, having non-trivial implications on how we design power delivery and implement designs today. Lastly, the rapid growth in computing demand in the era of AI/ML has translated into new workloads that stress the underlying devices very uniquely and demand different levels of guarantee; design-for-reliability is imperative for “always-on” applications like High-Performance-Compute and mission-critical applications such as autonomous drive. Device-level understanding and faithful modeling of both, the physical effects such as aging, time-dependent-dielectric breakdown, etc., as well as electrical mechanisms that cause transient errors in design is paramount. Aging effects at the device level are typically combated by guard banding at the design level; bias-temperature-instability (BTI) aging effects and electromigration of wires that have “healing” capabilities could be offset by balancing bias states in design. Effects such as hot-carrier-injection (HCI) that cause damage to the drain of the transistor cannot be compensated for at the design level and the time-to-failure is modeled in such cases. For transient errors (soft errors) that could corrupt stored data due to particle strikes, novel circuit design techniques are utilized to reduce their probability; for example, a “popular vote” scheme could be used by replicating logic and strategically spacing them apart; however, this would have a negative implication on the design area. Hence it is key to determine which part of the design is most affected by such faults that are heavily workload dependent. Additionally, memory blocks, flip flops, and logic blocks are uniquely impacted by such faults requiring different compensating techniques. In this talk, a brief overview of the physical and electrical failure mechanisms at advanced nodes will be provided. Popular modeling and design practices for handling the reliability of modern designs shall be discussed and trends will be reviewed highlighting the importance of design-technology-reliability-co-optimization techniques to enable future designs.

Electromigration (EM) effects are a high concern in power delivery networks where the current flow is unidirectional. As the integrated circuits (IC) technology nodes become smaller, the EM effects become a critical reliability failure mechanism also on signal nets. Such effect is also known as AC electromigration. This work presents a design strategy using special signal non-default routing rules (SSNDRs) to re-route the wire segments of critical nets that present a high current density and are EM-unsafe. Some EM-aware design steps are added in the traditional design flow to analyze, fix and improve the Mean Time to Failure (MTTF) of the designs.

This paper proposes a new power-ground (P/G) network sizing technique based on the recently proposed fast electromigration (EM) immortality check method for general multisegment interconnect wires and a new physics-based EM assessment technique for more accurate time to failure analysis. This paper first shows that the new P/G optimization problem, subject to the voltage IR drop and new EM constraints, can still be formulated as an efficient sequence of linear programing problem, where the optimization is carried out in two linear programing phases in each iteration. The new optimization will ensure that none of the wires fail if all the constraints are satisfied. However, requiring all the wires to be EM immortal can be overconstrained. To mitigate this problem, the first improvement is by means of adding reservoir branches to the mortal wires whose lifetime cannot be made immortal by wire sizing. This is a very effective approach as long as there is a sufficient reservoir area. The second improvement is to consider the aging effects of interconnect wires in the P/G networks. The idea is to allow some short-lifetime wires to fail and optimize the rest of the wires while considering the additional resistance caused by the failed wire segments. In this way, the resulting P/G networks can be optimized, such that the target lifetime of the whole P/G networks can be ensured and will become more robust and aging-aware over the expected lifetime of the chip. Numerical results on a number of IBM and self-generated power supply networks demonstrate that the new method can effectively reduce the area of the networks while ensuring immortality or enforcing target lifetime for all the wires, which is not the case for the existing current-density-constrained optimization methods.

The substantial increase in market demand for handheld devices drives the need for low-power high-speed data access SRAM for systems-on-chip (SoCs). In this paper, we present a novel low-power SRAM architectural design that provides high-noise margin double data rate (DDR) read/write accesses using a conventional 8T-Cell and a partitioned architectural structure consisting of even and odd modules (corresponding to even and odd addresses), which are accessed alternatingly. Write accesses occur at both clock edges such that the even modules are accessed at the rising edge and the odd modules are accessed at the falling edge. Similarly, the read accesses occur at both clock edges such that the even modules are assumed to be evaluated at the rising clock edge, while concurrently the odd modules are pre-charged, and vice versa. We implement a 128-bit × 64-bit SRAM with DDR accesses and an 8T-Cell structure using a standard 0.09μm/1V CMOS TSMC process. Simulation results reveal that our architecture operates with a 1GHz read/write cycle, a data throughput of 2GHz/64-bit, and an average power consumption of 23.4mW.