Accurate Instruction-Level Alias Analysis for ARM Executable Code

To function on programs written in languages such as C that make extensive use of pointers, automated software engineering tools require safe alias information. Existing alias-analysis techniques that are sufficiently efficient for analysis on large software systems may provide alias information that is too imprecise for tools that use it: the imprecision of the alias information may (1) reduce the precision of the information provided by the tools and (2) increase the cost of the tools. This paper presents a flow-insensitive, context-sensitive points-to analysis algorithm that computes alias information that is almost as precise as that computed by Andersen’s algorithm — the most precise flow- and context-insensitive algorithm — and almost as efficient as Steensgaard’s algorithm — the most efficient flow- and context-insensitive algorithm. Our empirical studies show that our algorithm scales to large programs better than Andersen’s algorithm and show that flow-insensitive alias analysis algorithms, such as our algorithm and Andersen’s algorithm, can compute alias information that is close in precision to that computed by the more expensive flow- and context-sensitive alias analysis algorithms.

Randomized self-routing algorithms for Clos networks

Memory access has proven to be one of the bottlenecks in modern architectures. Improving memory locality and eliminating the amount of memory access can help release this bottleneck. We present a method for link-time profile-based optimization by reordering the global data of the program and modifying its code accordingly. The proposed optimization reorders the entire global data of the program, according to a representative execution rate of each instruction (or basic block) in the code. The data reordering is done in a way that enables the replacement of frequently-executed Load instructions, which reference the global data, with fast Add Immediate instructions. In addition, it tries to improve the global data locality and to reduce the total size of the global data area. The optimization was implemented into FDPR (Feedback Directed Program Restructuring), a post-link optimizer, which is part of the IBM AIX operating system for the IBM pSeries servers. Our results on SPECint2000 show a significant improvement of up to 11% (average 3%) in execution time, along with up to 97.9% (average 83%) reduction in memory references to the global variables via the global data access mechanism of the program.

Probabilistic Look-ahead Contingency Analysis Integration with Commercial Tool and Practical Data

(2006). Probability and Computing: Randomized Algorithms and Probabilistic Analysis. Journal of the American Statistical Association: Vol. 101, No. 473, pp. 395-396.

Computer memory reduction through Fortran higher level language, discussing tradeoff between costs saved and additional logic hardware

Machine learning (ML) is revolutionizing image-based diagnostics in pathology and radiology. ML models have shown promising results in research settings, but the lack of interoperability between ML systems and enterprise medical imaging systems has been a major barrier for clinical integration and evaluation. The DICOM® standard specifies information object definitions (IODs) and services for the representation and communication of digital images and related information, including image-derived annotations and analysis results. However, the complexity of the standard represents an obstacle for its adoption in the ML community and creates a need for software libraries and tools that simplify working with datasets in DICOM format. Here we present the highdicom library, which provides a high-level application programming interface (API) for the Python programming language that abstracts low-level details of the standard and enables encoding and decoding of image-derived information in DICOM format in a few lines of Python code. The highdicom library leverages NumPy arrays for efficient data representation and ties into the extensive Python ecosystem for image processing and machine learning. Simultaneously, by simplifying creation and parsing of DICOM-compliant files, highdicom achieves interoperability with the medical imaging systems that hold the data used to train and run ML models, and ultimately communicate and store model outputs for clinical use. We demonstrate through experiments with slide microscopy and computed tomography imaging, that, by bridging these two ecosystems, highdicom enables developers and researchers to train and evaluate state-of-the-art ML models in pathology and radiology while remaining compliant with the DICOM standard and interoperable with clinical systems at all stages. To promote standardization of ML research and streamline the ML model development and deployment process, we made the library available free and open-source at https://github.com/herrmannlab/highdicom.

ion called Resilient Distributed Datasets (RDDs) [88]. RDDs is proposed to let programmers perform in-memory computations on large clusters in a fault-tolerant manner. This abstraction is motivated by two types of applications: iterative algorithms and interactive data mining tools that current computing frameworks handle inefficiently. As the cost of implementing machine learning algorithms as low-level MapReduce jobs on varying data and machine cluster sizes can be prohibitive, SystemML [89] is proposed to express machine learning algorithms in a higher-level language which are Scala. http://www.scala-lang.org. 56 compiled and executed in a MapReduce environment. MLbase [90] is a scalable machine learning system for both end-users and machine learning researchers. Two main functions are provided by MLbase: it enables machine learning researchers to implement scalable machine learning methods without requiring deep system knowledge; it provides a novel optimizer to select and dynamically adapt the choice of learning algorithms. Similar to SystemML, MLbase applies simple declarative way to specify machine learning tasks.

The goal of white-box cryptography is to implement cryptographic algorithms securely in software in the presence of an adversary that has complete access to the software’s program code and execution environment. In particular, white-box cryptography needs to protect the embedded secret key from being extracted. Bos et al. (CHES 2016) introduced differential computational analysis (DCA), the first automated attack on white-box cryptography. The DCA attack performs a statistical analysis on execution traces. These traces contain information such as memory addresses or register values, that is collected via binary instrumentation tooling during the encryption process. The white-box implementations that were attacked by Bos et al., as well as white-box implementations that have been described in the literature, protect the embedded key by using internal encodings techniques introduced by Chow et al. (SAC 2002). Thereby, a combination of linear and non-liner nibble encodings is used to protect the secret key. In this paper we analyse the use of such internal encodings and prove rigorously that they are too weak to protect against DCA. We prove that the use of non-linear nibble encodings does not hide key dependent correlations, such that a DCA attack succeeds with high probability.

A simple algorithm for reduced-state sequence estimation on channels with intersymbol interference is presented. The algorithm is based on the conventional Viterbi algorithm. The number of states is reduced by discarding trellis-paths based on their (modified) path metric and the minimum Euclidean distance in the trellis. An analysis of the error-event probability shows that the algorithm achieves performance of the maximum likelihood sequence estimator at high signal-to-noise ratios. The computational complexity and memory requirements of the algorithm are derived, the implementation of the algorithm is described in detail and simulation results for a severe ISI channel are provided.

The role of smart meters in the smart cities is becoming increasingly important. These smart meters are always connected to the network and this connectivity may leads to security risks. And, blockchain (BC) technology has recently received a lot of attention due to its data security stability and a distributed platform. BC has been applied to a plethora of different applications. However, BC requires high performance to be applied directly to a smart meter, which is an Internet of Things (IoT) device with low memory and slow CPU computation power. And, it cannot be scale up easily due to the nature of the distributed system. In order to compensate for this shortcoming, we propose a lightweight smart meter framework using BC technology, which is scalable and requires low computation power. In this proposed framework, data blockchain (dBC) and meta blockchain (mBC) are divided, and smart meters are divided into small groups to support scalability. The two proposed grouping algorithms are a delay-aware grouping algorithm that considers network delay and a random grouping algorithm that can improve security with a randomness. We also propose a new Enhanced Privacy Piggy Bank Protocol (EPPB) using bilinear pairing of cryptographic keys to authenticate the communicating parties for smart meters. We presented simulation results and security analysis to verify our proposed framework. From this simulation results, we can see that even if the number of smart meters increases, the performance is not affected.

Email thread sentiment sequence identification using PLSA clustering algorithm

Probabilistic bits, or p‐bits, represent a novel computational element that bridges the gap between deterministic classical bits and quantum bits (qubits) used in quantum computing. Unlike classical bits that maintain a definite state of 0 or 1, a p‐bit fluctuates between these states in a controlled, stochastic manner. This probabilistic behavior allows for the representation and processing of information in a form that leverages inherent randomness. In this study, a unique approach is presented to generating p‐bits using a hybrid conjugated polymer, poly‐4‐((6‐(4H‐dithieno[3,2‐b:2',3'‐d]pyrrol‐4‐yl)hexyl)oxy)‐N,N‐diphenylaniline (pTPADTP), as a memristive material. The polymer's conjugated backbone, combined with pendant triphenylamine groups, enables the creation of p‐bits through random resistance switching. The stochasticity of this polymeric memristor makes it particularly suited for p‐bit applications in stochastic optimization, probabilistic algorithms, and artificial neural networks. The charge transport in the polymer is facilitated by two synergistic percolation mechanisms: one occurring along the polymer backbone and the other through the pendant triphenylamine groups. The study of p‐bits generated from pTPADTP opens new avenues for advancing both the theory and practice of computation, where uncertainty and randomness are harnessed as valuable computational resources.

As artificial intelligence is gaining popularity, its energy use keeps increasing. This thesis offers progress towards a possible mitigation strategy to this, in the form of analog in-memory computing, whereby multiplication can be performed directly in the computer memory. This requires nonbinary memory elements, e.g. cells that can store values ranging from 0 to 1000 instead of standard binary computer memory that can store only 0 or 1. In addition, these cells should not lose their information over time or require energy input to keep their information.<br/><br/>Phase-change memory is a promising technology that satisfies those requirements. It relies upon a phase-change material, the atomic configuration of which can be reversibly switched between ordered (crystalline, high conductance) and disordered (amorphous, low conductance). Based on the amount of disordered material, the conductance can be tuned to many values.<br/><br/>In the first part of this thesis, a phase-change material consisting of antimony with a very small amount of germanium (approximately 5 atomic percent) is investigated as fabricated and after switching. While its low switching energy and high operating temperature are promising for use in in-memory computing, its low switching endurance is a significant drawback.<br/><br/>In the second part of the thesis, a novel phase-change memory device architecture is presented, showing excellent performance with respect to switching energy, amount of storable values, and read noise. The so-called disc-type device uses an extremely thin circular phase-change material layer (5 nanometers thick), a small electrode in the center, and a perimeter electrode to achieve this.

Transactional Memory (TM) is promising to make parallel programming easier. There have been many hardware implementations of transactional memory (HTM) proposed to improve the performance, but they still suffer from some overheads when a transaction commits or aborts. So, we have been developing a novel new HTM design, called DCTM, which enables transactions of arbitrary size to commit or abort in a fixed number of cycles -- typically one cycle. DCTM stores values of data modified in a transaction into an L1 cache. Each cache checks the conflict between transactions through the bus snooping every time another cache broadcasts a transactional modification of data, and so, when a transaction commits, other concurrent and conflicting transactions can abort immediately. The sophisticated cache coherency control of DCTM can permit multiple caches to contain their own dirty lines of the same memory address. This feature enables a committing transaction to publish all of data modified in the transaction at once, while it leaves them in its local cache. The cache broadcasts only a simple signal of committing, and doesn't write back nor send any other signal for cache coherency. DCTM delays the write-back of such left data -- with merging to an up-to-date line data when there are multiple dirty lines of the same address in the system -- into main memory until the data is accessed again. In this paper, we refine the implementation of DCTM and present the detailed design of the cache control. As a simulation result, DCTM achieves the performance improvement of 1.1~79.7% in comparison to a TM system which detects conflicts when a transaction tries to commit.