Accurate transmission line characterization on high and low-resistivity substrates

The measured photocurrents from two different p-n-junction silicon photodiodes at 170-Å (73-eV) and at 8.34-Å (1480-eV) light are presented. One is a standard extreme-UV photodiode fabricated on low resistivity silicon (70-100 Ω cm), and the other is fabricated on high-resistivity silicon (> 2 × 10(4) Ω cm). The photocurrents from the diode on high-resistivity silicon are at least an order of magnitude greater than the photocurrents from the diode on low-resistivity silicon when a reverse bias of 40 V is applied to each. This photocurrent enhancement is 15.4 ± 4 at 8.34 Å and 12.5 ± 2 at 170 Å.

This paper presents experimental results for line-to-line coupling between adjacent coplanar waveguide (CPW) transmission lines. The CPW lines are fabricated on glass and low resistivity CMOS grade Si substrates coated with a 20/spl mu/m cyclotene polymer. From the measurement results it is found that the coupling increases with frequency on low resistivity silicon substrate while the coupling on glass shows relatively constant peaks. A spacing of 600/spl mu/m between CPW lines is required to avoid parasitic coupling less than 30dB for frequencies up to 30GHz when fabricated on low resistivity silicon, while a spacing of 200/spl mu/m is required when fabricated on glass. The conductor width (W) and the slot width (S) for low resistivity silicon is 80/spl mu/m and 45/spl mu/m, and on the glass substrate W = 150/spl mu/m, S = 30/spl mu/m. Based on full-wave EM simulation results, it is argued that the primary coupling mechanism is through the interaction of higher-order modes.

In this paper, technological solutions based on the use of thick low-k polymer layers on low-resistivity (LR) silicon substrate have been investigated. These thick organic layers provide an insulation of interconnects and passives circuits from the lossy silicon substrate and thus minimize its dramatic impact on the performances. Different thicknesses of polymer layer have been tested. Both EM-simulations and high-frequency characterizations have shown an important benefit in coplanar waveguide performances by employing a large polymer thickness (30 /spl mu/ in our case). A noticeable increase of the Q-factor close to 16% has been achieved with burying the realized CPW lines into a quasi-homogeneous polymer medium.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper reports the theoretical and experimental studies of high-<formula> <tex>$Q$</tex></formula> suspended microinductors produced by flip-chip assembly for multigigahertz RF integrated-circuit applications. The effects of device and substrate parameters on the <formula formulatype="inline"><tex>$Q$</tex> </formula> factor of the inductor devices are studied by numerical simulation using Ansoft's High Frequency Structure Simulator electromagnetic field simulation package. Suspended inductor devices are realized using a flip-chip assembly method in which the inductor structures with the supporting pillars are fabricated on a low-cost polyimide thin-film carrier and then assembled onto a low resistivity (3–4 <formula formulatype="inline"><tex>$\ \Omega\,\cdot\,$</tex></formula>cm) silicon substrate by flip-chip bonding. Individual and 2<formula formulatype="inline"> <tex>$\,\times\,$</tex></formula>2 arrays of meander and spiral inductor designs have been successfully fabricated with air gap heights ranging from 15 to 31 <formula formulatype="inline"><tex>$\mu$</tex></formula>m. Maximum <formula> <tex>$Q$</tex></formula> factors of <formula formulatype="inline"><tex>${\sim}$</tex> </formula>15 and <formula formulatype="inline"><tex>${\sim}$</tex></formula>13 at <formula formulatype="inline"><tex>${\sim}$</tex></formula>1 GHz have been achieved for meander and spiral suspended inductor devices before pad deembedding. It is shown that the optimal air gap between the inductor and substrate surface is <formula formulatype="inline"><tex>${\sim}{\hbox{15}}\ \mu$</tex></formula>m beyond which no further enhancement in the <formula formulatype="inline"> <tex>$Q$</tex></formula> factor can be obtained for devices on low-resistivity substrates. The experimental results are in excellent agreement with that of theoretical simulation. The inductor assembly method requires minimal chip/wafer processing for integration of high-<formula><tex>$Q$</tex></formula> inductors. </para>

A micromachining process has been developed to create high impedance and low loss high aspect ratio coplanar waveguide (HARC) on low resistivity silicon. The process uses silicon DRIE to create an array of tall mesas that are spaced with a precise pitch. The silicon mesa array is then merged into a single solid SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> mesa using thermal oxidation. The solid SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> mesa creates a wide dielectric for use in high impedance HARC. The complete fabrication process includes DRIE, thermal oxidation, electroplating, planarization, and substrate removal to create HARC on low resistivity silicon with a planar surface. A high impedance HARC has been fabricated on silicon using this method. Measurements show that silicon substrate removal increases the line impedance from 20 Ω to 57 Ω, reduces effective dielectric constant from 6 to 2, and reduces attenuation constant from 33 dB/cm to 4 dB/cm @ 30 GHz. Measurements are compared to an analytical model derived for HARC.

This paper presents the fabrication process of a thin suspended membrane on normal low resistivity silicon (LRSi), which is then utilized to design millimeter-wave (mm-wave) transmission line and passive circuits with low loss. First, two redistribution metal layers are formed on a plain LRSi wafer with benzocyclobutene in-between. Then, the wafer is thinned down and etched from backside with a specific pattern. Based on this process, a volume is introduced underneath the front side structure and the lossy LRSi substrate is replaced by air, which is the ideal substrate with no loss. Using this method, the substrate loss that contributes the majority part of total loss in mm-wave circuits on LRSi is eliminated. As the operating frequency goes into mm-wave region, the circuit size is scaled down so that the suspended portion is so small that it will not increase the mechanical instability of the structure. Therefore, the proposed suspended membrane on LRSi technology provides an excellent platform to construct mm-wave components. A U-shaped slotline resonator formed on the first redistribution layer is proposed and its quality factors are studied in detail. A second-order bandpass filter is designed and implemented by cascading two such U-shape slotline resonators. The measured frequency responses exhibit good filtering performance, with fractional bandwidth of 13.9% at 126.8 GHz, midband insertion loss of 3.9 dB and passband return loss larger than 14.2 dB. It demonstrates that the proposed suspended membrane on LRSi technology is an excellent candidate for designing low loss mm-wave components.

Alloying contacts to gallium arsenide by hot hydrogen and HCl gases

Accurate characterization and modeling of microwave active devices is a prerequisite for reliable microwave circuit design. A new silicon micro-test-fixture which offers the possibility of (re-)using accurately characterized microwave GaAs FETs in final circuits is presented. In this way, device tolerances are eliminated resulting in accurately predictable microwave performances. The technological requirements that must be fulfilled to facilitate the re-usability of commercially available GaAs FET transistor chips and the required processing procedure are discussed. For device characterization purposes, microtest-fixtures are micromachined on a high resistivity silicon (MRS) wafer which is also suitable as a microwave substrate. After characterization and modeling of the microwave device, the required passive circuitry for the intended application can be realized on the same wafer incorporating the pre-tested device and using distributed coplanar components. The proposed technology minimizes the required lengths of bond wire interconnects between the chip and the passive circuit and offers the possibility of realizing planar interconnects using air-bridge technology.

ABSTRACTDiamond-based rectifiers are promising devices for the development of next-generation power electronics. However, presented device structures limit current operation as low as tens A, which hampers diamond from real industrial applications. One of the critical issues is poor availability of conductive (low-resistivity) substrates which can be used for vertical-type devices for high-output operations. Recently, we have successfully fabricated heavily boron-doped (p+) low-resistivity diamond by hot-filament chemical vapor deposition (HFCVD). Resistivity was monotonically decreased to 1.2 mΩcm with amount of doped boron. In this study, to further investigate potentials for electric applications, contact resistance between metal/p+ diamond was evaluated by transmission line model (TLM). From the current-voltage characteristics, low specific contact resistance of ∼10−7Ωcm2was demonstrated.

The authors present a new technique for fast calculation of dispersion characteristics in inhomogeneously loaded waveguides. The method calculates an approximate value of propagation constant at a desired frequency based on more accurate computations of the field distribution and propagation constant at a few selected frequency points. Numerical tests show that the relative error in propagation constant below 0.05% can easily be obtained throughout a very wide frequency band for a dominant mode using accurate data calculated at as few as four frequency points.

In this paper, a novel technological solution using both silicon surface micromachining and thick polymer layer deposition on low resistivity silicon substrate (20 /spl Omega//cm) has been investigated. The proposed structure achieves both a low attenuation level and a high quality factor. The silicon etching into the coplanar slots leads indeed to a noticeable decrease of the losses, whereas filling the gaps with the polymer BCB avoids a degradation of the effective permittivity.

This paper deals with a novel technological solution based on the use of surface micromachining in coplanar slots that are filled with a thick organic dielectric layer. This technique enables both Q factor and losses improvements of passive circuits realized on low resistivity silicon substrate. It permits indeed to achieve much better attenuation level without an important decrease of the effective permittivity.

Novel CMOS monolithic pixel detectors designed at KEK and fabricated at Lapis Semiconductor in 0.2 μm Silicon-on-Insulator (SOI) technology are presented. A thin layer of silicon oxide separates high and low resistivity silicon layers, allowing for optimization of design of detector and readout parts. Shallow wells buried under the oxide in the detector part screen the entire pixel electronics from electrical field applied to the detector. Several integration type SOI pixel detectors have been developed with pixel sizes 8–20 μm. The general features of 14 × 14 μm2 detectors designed on different wafers (CZ-n, FZ-n and FZ-p) were measured and compared. The detector performance was studied under irradiation with visible and infra-red laser, and also X-ray ionizing source. Using X-rays from an Am-241 source the noise of readout electronics was measured at different working conditions, showing the ENC in the range of 88–120 e−. The pixel current was calculated from average DC pedestal shift while varying the pixel integration time. The operation of the detector was studied under partial and full depletion conditions. The effects of temperature and detector bias voltage on noise and leakage current were studied. Characteristics of an ADC integrated in the front-end chip are also presented.

A pre‐process gettering treatment is described for Czochralski silicon substrates which removes essentially any transition group metal contaminants present in the wafer and continues to getter contaminants during subsequent device processing. Laser induced damage (LID) on the back surface of the wafer, a modified high temperature treatment, and formation of oxygen precipitates in the bulk of the wafer only, are used as a three‐step gettering process. Neutron activation analysis (NAA) was used to monitor the gettering behavior of each individual contaminant species and shows that the combined treatment is indeed nearly 100% effective in removing impurities, both from starting substrates and from processed wafers. Removal of impurities from the starting substrates is important in order to prevent the formation of oxidation induced stacking faults (OSF), which are nucleated by impurities and then become decorated with impurities making them much harder to getter (1). Holdtime performance of 4K and 16K dynamic RAM's fabricated on substrates treated in this manner served to evaluate the effectiveness of the treatment. Significant improvement can be achieved for bulk substrates. However, the performance of epitaxial silicon on low resistivity substrates cannot be matched since the low resistivity substrate in the EPI case additionally suppresses the minority carrier diffusion current from the bulk of the wafer. The individual steps of the treatment are: (i) produce laser induced damage on the back surface of the wafers by means of powerful, partially overlapping laser pulses; (ii) ramp from 950° to 1250°C in 0.5% , 0.5% , balance argon; (iii) oxidize at 1250°C for 8 hr in dry , then ramp down to 950°C. Keeping the oxygen concentration to 0.5% during step (ii) is important to prevent formation of a thick oxide film during this step. The long oxidation at 1250°C both depletes interstitial oxygen at the Si surface, thus preventing formation of OSF, and causes formation of oxygen precipitates in the bulk if the initial concentration is high enough. Oxygen precipitates in the bulk are a valuable means of gettering.

Thin pad detectors made from 75 μm thick epitaxial silicon on low resistivity substrate were irradiated with reactor neutrons to fluences from 2.5× 1016 n/cm2 to 1× 1017 n/cm2. Edge-TCT measurements showed that the active detector thickness is limited to the epitaxial layer and does not extend into the low resistivity substrate even after the highest fluence. Detector current was measured under reverse and forward bias. The forward current was higher than the reverse at the same voltage but the difference gets smaller with increasing fluence. Rapid increase of current (breakdown) above ∼ 700 V under reverse bias was observed. An annealing study at 60̂C was made to 1200 minutes of accumulated annealing time. It showed that the reverse current anneals with similar time constants as measured at lower fluences. A small increase of forward current due to annealing was seen. Collected charge was measured with electrons from 90Sr source in forward and reverse bias configurations. Under reverse bias the collected charge increased linearly with bias voltage up to 6000 electrons at 2.5× 1016 n/cm2 and 3000 electrons at 1× 1017 n/cm2. Rapid increase of noise was measured above ∼ 700 V reverse bias due to breakdown resulting in worse S/N ratio. At low bias voltages slightly more charge is measured under forward bias compared to reverse. However better S/N is achieved under reverse bias. Effective trapping times were estimated from charge collection measurements under forward bias showing that at high fluences they are much longer than values extrapolated from low fluence measurements—at 1× 1017 n/cm2 a factor of 6 larger value was measured.