Achieving High Test Quality with Reduced Pin Count Testing

Over the last 2-3 years, there has been a major change in the IC industry from being predominantly to being predominantly (for new design starts). The question has now changed to: can we completely avoid functional testing? The same trends that are driving companies toward scan-based testing will also drive them to completely avoid functional-based testing. The advantages of structural testing cannot be fully exploited unless at-speed functional testing is avoided. The move away from functional testing will happen in stages. Some companies are already avoiding functional test for some test insertions - but not all. For example, some products are currently tested with scan-based, reduced pincount testing at wafer level - but still require full pincount, scan+functional testing at package test.

High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fill (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing.

This paper discusses the aspects and associated requirements of design and implementation of at-speed scan testing. It also demonstrates some important vector generation and implementation procedures based on a real design. An innovative method of scan pattern timing creation based on the results from static timing analysis is presented. The paper also describes the usage of a clock control module on J750 tester, which creates fast clock by combining two tester channels with high edge placement accuracy. These methods allow a short test pattern preparation time and the use of low-cost test equipment, while providing the high quality at-speed testing.

Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization criterion. An effective path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.

In order to generate correct at-speed scan patterns, the effect of timing exceptions and constraints needs to be considered during test generation. A path-oriented approach to handle timing exception paths during at-speed ATPG has been presented in (Vorisek et al., 2006). The new method has been applied to and tested on many example circuits at Semiconductor Technology Academic Research (STARC). This paper presents a sample of these test cases, and illustrates how the proposed method generates correct-by-construction at-speed patterns on these circuits without pessimism

At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-test. However, due to their reliance on random patterns, current logic BIST techniques are not able to deal with large designs without adding high test overhead. In this paper, we propose a functional self-test technique that is deterministic in nature. By targeting the structural test need of manageable components with the aid of processor functionality, this technique has the fault coverage advantage of deterministic structural testing and the at-speed advantage of functional testing. Most importantly, by relieving testers from test application, it enables at-speed testing of GHz processors with low speed testers. We have demonstrated our methodology on a simple accumulator-based microprocessor. The results show that with the proposed technique, we are able to apply high-quality at-speed tests with no test overhead.

Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects (Campregher et al., 2005). We propose a number of changes to the detailed routing architecture of island-style FPGAs to tolerate multiple random, distributed interconnect defects without re-routing and with minimal impact on signal timing. Our scheme is a user option prebuilt into an architecture, requiring +11% area for additional multiplexers. Unused (spare) wiring tracks are also needed, bringing total overhead to 24% to tolerate stuck-at or open faults, or 34% to include bridging. User circuits that do not fully stress the routing network already have these tracks freely available. The delay penalty is programmable: 5-10% if defect rates are expected to be sufficiently low, but can be as high as 25% if defect rates are high. Our schemes can tolerate more than 10 interconnect defects for large array sizes of 128 /spl times/ 128. Unlike row/column redundancy schemes, our schemes are scalable: they naturally tolerate more defects as the FPGA array size increases. This work is the first detailed analysis of fine-grained defect-tolerant schemes in FPGAs.

This paper describes a comprehensive off-line system level test strategy developed for several complex high speed, telecom chips. These chips feature a large number of clocks, mixed analog and digital logic and large high speed RAMs. The test strategy was based on the principles of hierarchical test, DFT reuse, BIST and at-speed test, and was implemented using DFT solutions provided by Logic Vision. The paper further specifies the requirements for integration of the DFT solutions within the ASIC vendor's flow. The final DFT implementation which includes scan, at-speed Logic BIST, RAM BIST, PLL BIST, user-defined IEEE 1149.1 TAP and Boundary Scan with fault insertion capability, is presented The system level test architecture focusing on an in-house developed TAP Master is given. Motivation from a cost saving perspective in system SW development and improved system quality monitoring are highlighted as major driving forces in support of this strategy. Finally, some practical issues for consideration when planning system test based on BIST are presented.

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.

Most previous DFT-based techniques for low-capture-power broadside testing can only reduce test power in one of the two capture cycles, launch cycle and capture cycle. Even if some methods can reduce both of them, they may make some testable faults in standard broadside testing untestable. In this paper, a new test application scheme called partial launch-on-capture (PLOC) is proposed to solve the two problems. It allows only a part of scan flip-flops to be active in the launch cycle and capture cycle. In order to guarantee that all testable faults in the standard broadside testing can be detected in the new test scheme, extra efforts are required to check the overlapping part. In addition, calculation of the overlapping part is different from previous techniques for the stuck-at fault testing because broadside testing requires two consecutive capture cycles. Therefore, a new scan flip-flop partition algorithm is proposed to minimize the overlapping part. Sufficient experimental results are presented to demonstrate the efficiency of the proposed method.

Trichloroethylene (TCE), a common occupational solvent and groundwater contaminant, has been associated with a variety of immunotoxic effects and may be associated with an increased risk of non-Hodgkin lymphoma (NHL). Altered serum immunoglobulin levels have been reported in NHL patients and in animals exposed to TCE. Recently, we reported that occupational exposure to TCE is associated with immunosuppressive effects and immune dysfunction, including suppression of B cell counts and activation, even at relatively low levels. We hypothesized that TCE exposure would also affect immunoglobulin levels in humans. We measured serum levels of IgG, IgM, and IgE, by ELISA, in TCE-exposed workers (n=80) and unexposed controls (n=45), matched by age and gender, in a cross-sectional, molecular epidemiology study of occupational exposure to TCE in Guangdong, China. Personal exposure measurements were taken using 3 M organic vapor monitoring badges over a three-week period before blood collection. Workers exposed to TCE had about a 17.5% decline in serum levels of IgG compared to unexposed controls (p for exposed vs. unexposed = 0.0002). Similarly, serum levels of IgM were reduced by about 38% in workers exposed to TCE (p for exposed vs. unexposed < 0.0001). Serum levels of both IgG and IgM were significantly decreased in workers exposed to < 12 ppm of TCE, the median exposure level. Adjustment for B cell counts and other potential confounders had minimal impact on our findings. IgE levels were not significantly different between exposed and control subjects. These results are consistent with in vivo observations and provide further evidence that TCE is immunotoxic at relatively low exposure levels, and provide additional biologic plausibility to the reported association of TCE with NHL. Citation Format: Luoping Zhang, Bryan Bassig, Joseph L. Mora, Roel Vermeulen, Yichen Ge, John D. Curry, Wei Hu, Min Shen, Chuangyi Qiu, Zhiying Ji, Boris Reiss, Cliona McHale, Songwang Liu, Weihong Guo, Mark Purdue, Fei Yue, Laiyu Li, Martyn T. Smith, Hanlin Huang, Xiaojiang Tang, Nathaniel Rothman, Qing Lan. Alterations in serum immunoglobulin levels in workers occupationally exposed to trichloroethylene. [abstract]. In: Proceedings of the AACR Special Conference on Post-GWAS Horizons in Molecular Epidemiology: Digging Deeper into the Environment; 2012 Nov 11-14; Hollywood, FL. Philadelphia (PA): AACR; Cancer Epidemiol Biomarkers Prev 2012;21(11 Suppl):Abstract nr 44.

A typical design today is implemented with DFT where the capture clocks are supplied on chip. The on-chip controller (OCC) plays a critical role in the application and the quality of the tests. Almost every design house has developed an innovative way of delivering either the structural tests or in house mix of structural-functional tests through the use of OCC and the design-for-test (DFT) implemented on the chip. Complexities in the implementation come due to the various test strategies employed with: • Process variation leading to issues like dealing with non-unique critical paths on every chip • Test data compression becoming primary DFT solution for manufacturing test • Low cost testers unable to keep up with the requirements of clocking schemes In this session, we want to explore the current offerings of the EDA tools to implement OCC based solutions and how the industry is going beyond those standard solutions to use innovative OCC based tests to provide a quality at-speed manufacturing test solution.

Multicycle paths are commonly seen in today's high performance designs with multi-frequency clock domains. Previous methods either treat the multicycle paths as false paths and masking the transition on the paths, or slow down the clocks in order to test the multicycle paths. Both approaches would compromise the at-speed test quality. In this paper, we present an at-speed test methodology to target the faults on the multicycle paths using the same clock scheme as regular faults at the single cycle paths. The methodology takes SDC files which defines all timing exceptions and the clock frequency information and create at-speed pattern set that detects faults on both single and multicycle paths. The approach also handles all of the timing exceptions and constraints defined in SDC to prevent simulation mismatches. The experiment results on couple industrial designs demonstrate the effectiveness and efficiency of the proposed methodology to handle complex designs with large timing exception paths.

Efficient test and diagnosis methods are required to ensure high levels of dependability of the electronic systems deployed to the market. These methods involve a trade-off in terms of accessibility to test nodes, test stimuli complexity, area overhead, and data processing that, altogether determine the impact that the involved operations have in the final cost, performance, and reliability presented by these systems. The work presented here describes preliminary results obtained with the application of correntropy as a means to efficiently analyse test responses in the fault detection decision process.

An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip