Adaptive Digital Feedback Predistortion Technique for Linearizing Power Amplifiers

In this work, a Doherty power amplifier is presented for IMT-Advanced system at 450–470MHz frequency band. An imperfect Quarter-wave transmission line, which consisted of two shunt capacitors and a series microstrip line, is adopted to replace the bulky impedance inverter quarter-wave transmission line for designing the Doherty power amplifier (PA). Both the traditional and proposed structures for the Doherty power amplifiers were implemented. Comparing with the traditional Doherty amplifier, the size of the circuit and the manufacturing costs are decreased obviously. The measurement results of the proposed Doherty PA exhibit good performance as well as the traditional Doherty power amplifier. For a input signal with a 7.8dB Peak to Average Power Ratio (PAPR), the measured drain efficiency of the proposed Doherty power amplifier is 48.5% at an average output power of 43.0 dBm, which is a 7.8dB backed — off the peak output power. Moreover, in order to improve the linearity of the proposed Doherty power amplifier, the augmented Hammerstein and polynomial predistorter are used to linearize the proposed Doherty power amplifier. After digital predistortion, the adjacent channel leakage ratio (ACLR) reaches −45.5dBc at an average output power of 43.0 dBm, which can satisfy the requirements of the IMT-Advanced systems.

We have developed a novel digital feedback predistortion(DFBPD) linearization based on RF feedback PD for the wide bandwidth modulated signals. The wideband PD operation is carried out by combining the DFBPD and memory lookup table(LUT). To experimentally demonstrate the linearization performance of the proposed PD technique for wideband signal, a class-AB amplifier using an LDMOSFET MRF6S23140 with 140-W peak envelope power is employed at 2.345 GHz. For a forward-link 2FA wideband code-division multiple-access signal with 10 MHz carrier spacing, the proposed DFBPD with memory LUT delivers the adjacent channel leakage ratio at an 10 MHz offset of -56.8 dBc, while those of the amplifier with and without DFBPD are -43.2 dBc and -41.9 dBc, respectively, at an average output power of 40 dBm. The experimental result shows that the new DFBPD with memory LUT provides a good linearization performance for the signal with wide bandwidth.

An adaptive digital predistortion (PD) technique is proposed for linearization of power amplifiers (PAs) in multiple-input multiple-output (MIMO) transmitters. Instead of constructing a separate feedback path at each PA, we propose a PD technique based on a combined feedback, which adds all the PAs' outputs to form a single feedback. We develop an algorithm for finding the multiple PA characteristics jointly from the combined feedback. The PD parameters are calculated from the identified PA characteristics. Although the proposed method requires more computations for PA identification than the conventional method, its hardware implementation is much simpler and can overcome the crosstalk problem of a radio frequency (RF) selector, which is necessary for multiple feedback selection. The simulation results show that, despite its simple structure, the linearization performance of the proposed method is almost the same as the separate multiple feedback method.

A dual adaptive bias (DAB) control technique has been proposed for Doherty power amplifiers (DPAs) in mobile handsets to improve robustness against load variations in various operating environments. However, the practical deployment of this method has thus far been hindered by the operational complexity of establishing bias settings across varying power levels. In this study, we address these challenges by improving the feedback loop gain to enhance overall performance. Increasing loop gain introduces two main challenges, including amplified errors within the feedback loop and potential stability degradation. To mitigate these issues, we identify the drive level detector (DLD) as the primary source of errors and propose techniques to substantially reduce these errors. Furthermore, we propose a design methodology that ensures system stability without excessively compromising loop bandwidth. Our approach achieved a stable loop gain exceeding +5 dB at 100 MHz. The experimental results demonstrate that the proposed improvements effectively suppressed distortion at low power under varying load conditions and partially replaced manual bias tuning with fully automatic tuning. This method also improved DPA performance under nominal load. We achieved a power-added efficiency of 43.6% and an adjacent channel leakage ratio (ACLR) of −35 dBc using a 100 MHz bandwidth 5G signal without digital predistortion (DPD). The proposed methodology includes a quantitative evaluation of loop gain and provides clear guidelines to improve performance and enhance robustness. This approach shows promise for accelerating the commercialization of next-generation DPAs.

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

This letter reports a high-efficiency gallium nitride (GaN) high-electron mobility transistor (HEMT) Doherty power amplifier (DPA) based on the class-E topology for wideband code-division multiple-access (WCDMA) applications. The class-E topology is employed as the carrier and peaking cells of the Doherty configuration. For validations, the proposed DPA is designed and implemented with 25-W GaN HEMTs at 2.14 GHz. For the proposed DPA, the power-added efficiency (PAE) and drain efficiency of 56.1% and 61.2% are achieved at 40 dBm (6-dB backoff power from Psat) for a continuous wave. For a 1-carrier WCDMA signal, the PAE of 44.8% is obtained with an adjacent channel leakage ratio (ACLR) of -31 dBc at 37 dBm, which is an 8.9% improvement over the conventional DPA with an ACLR of -36.4 dBc.

This article presents a comprehensive design methodology for broadband Doherty power amplifiers (DPAs) based on an extended two-port <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S$</tex-math> </inline-formula>-parameter solution set and irregular matching networks. Instead of designing the carrier, peaking, and post-matching networks separately, the entire output combining network (OCN) is modeled as a single two-port network, which captures the real interaction and load modulation mechanisms that determine wideband Doherty performance. To enlarge the feasible design space, the optimal load impedances obtained from load-pull simulations are processed using polygonal Boolean operations to extract their common high-efficiency, high-power region, followed by Poisson-disk sampling to generate a diverse set of impedance candidates. These impedances are converted into a large <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S$</tex-math> </inline-formula>-parameter solution set, any of which is acceptable for proper Doherty load modulation. An irregular microstrip matching structure is introduced to provide additional degrees of freedom and enable direct layout-level optimization. A two-stage selection and joint optimization is then developed, where passive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$S$</tex-math> </inline-formula>-parameter matching and active large-signal performance are jointly used to guide the design. To validate the proposed approach, a 1.2–3.1GHz DPA with an 88.4% fractional bandwidth is designed and fabricated. Measurements show saturated output power above 43.1dBm, saturated efficiency of 51.8%–70.6%, and 6-dB back-off efficiency of 50.3%–55.6%. With digital predistortion (DPD), the adjacent channel leakage ratio (ACLR) is better than −50 dBc.

The sampling clock accuracy of the digital predistortion (DPD) feedback path is limited by nonideal electronic components, which introduces random clock jitter and thus degrades the linearization performance. In this paper, we propose a new DPD architecture capable of estimating and mitigating the sampling clock jitter. The theoretical analysis reveals that the sampling clock jitter has a adverse effect on the signal-to-noise ratio (SNR) of the samples received and hence degrades the DPD performance. By applying the proposed reference injection method, the clock jitter can be estimated and mitigated, effectively. Simulation results demonstrate that the proposed DPD architecture can improve the normalized mean square error (NMSE) and the adjacent channel leakage ratio (ACLR) performances, compared with conventional DPD architecture when feedback sampling clock jitter is considered.

This paper describes an adaptive digital predistorter (ADP) for RF power amplifier (PA) linearization using an adaptive neuro-fuzzy inference system (ANFIS). The ANFIS predistorter (PD) employs the advantage of real-time modeling of the PA's responses in determining the PD's functions. The amplitude and phase corrections for the PD are represented in an easy-to-understand fuzzy if-then rule, while the parameters involved in the fuzzy representation are trained using neural networks algorithms, namely gradient-descent and least squares estimate (LSE). Experimental results show that a 26.3-dB improvement in linearity for a two-tone signal is obtained, while a distorted WCDMA signal is suppressed by at least 12 dB. The adaptability of the ANFIS PD to instantaneous variation in PA responses through time is also demonstrated, and results show that the ANFIS PD is capable of adapting to simulated environmental changes, which is a topic often omitted by researchers in this area. Further testing demonstrated that the tuning parameters involved in the training could be reduced by more than half for a fairly nonlinear PA without significantly degrading the suppression capability.

This letter presents a bias-adjusted group digital predistortion (DPD) method to enhance linearization in multiple-input multiple-output (MIMO) transmitters with hybrid beamforming. By introducing a cross-normalized mean square error (CNMSE) metric, the nonlinearity consistency of multiple Doherty power amplifiers (DPAs) sharing radio frequency (RF) chains is quantitatively evaluated. A reference state is established using the worst-performing DPA, and the gate biases of other DPA are optimized to minimize CNMSE, aligning their nonlinear characteristics. This simplifies DPD training to a single-channel paradigm. Experiments with four DPAs under a 64-quadrature amplitude modulation (QAM) signal (200 MHz bandwidth) demonstrate a 6.77 dB adjacent channel power ratio (ACPR) improvement over the baseline and 4.51 dB gain versus conventional DPD, validating efficient multi-DPA linearization for resource-constrained MIMO systems.

The paper presents the results of laboratory studies on influence of DC transistor operating conditions both on power amplifier (PA) linearity and effectiveness of digital predistortion procedure. The impact of DC operating conditions of 10 W GaN HEMT power amplifier on nonlinearity factors without and with digital predistortion (DPD) were investigated. The obtained results show that there is an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor. However, some noticeable improvement of ACLR with significant increase in PA power added efficiency (PAE) is obtained for PA with digital predistortion.

In this paper, a novel modified Doherty power amplifier (DPA) that allows for extended output back-off (OBO) range, improved power utilization factor (PUF), and increased peak power over a broad bandwidth is proposed. It starts with an in-depth analysis of the modified DPA circuitry that first revealed the ability to control the impedances seen by the main transistor versus frequency by properly setting the magnitude and phase of the ratio between the peaks of the combining currents. This is then exploited to maximize the peak power and enhance the achievable bandwidth. Furthermore, a complex-to-real output matching network is incorporated in the auxiliary path and its parameters are carefully chosen to produce proper load modulation while satisfying the required peak combining current ratio. For validation purpose, a DPA prototype is designed to operate over the frequency range of 1.35-2.05 GHz with an OBO of 9 dB. Under the continuous-wave excitation, the DPA prototype maintained the drain efficiency (DE) of 52%-55% and 65%-75% at 9-dB OBO and peak power, respectively, over the entire targeted band. In addition, the measured peak power and PUF were about 42 dBm and higher than 0.9, respectively. The linearizability of the DPA prototype using digital predistortion (DPD) with memory was assessed while being driven with a 40-MHz carrier-aggregated signal with a peak-to-average power ratio of 8.9 dB and at an average output power of 33 dBm. When the carrier frequency is swept over the entire band, the measurement revealed an adjacent channel leakage ratio of better than -46.5 dBc after DPD with an average DE of 49.3%-53%.

This paper presents adaptive phase-only memory digital pre-distortion (DPD) and gain/phase/delay imbalance correction techniques for outphasing power amplifiers (PAs). Least squares adaptation is used for the phase-only DPD and imbalance correction techniques. The performance of these techniques is verified by co-simulations and measurements of an outphasing PA implemented with two identical class-F PAs and a Chireix combiner. The Chireix combiner with compensating stubs added to achieve high efficiency introduces nonlinearity. The proposed adaptive phase-only memory DPD corrects for the nonlinearity due to the Chireix combiner. The proposed gain/phase/delay imbalance correction technique achieves total lower/upper adjacent channel power ratio (ACPR) improvements of 43.8/37.6 dB for 5-MHz and 46.2/38.3 dB for 10-MHz long-term-evolution signals in measurements. The fractional-sample delay imbalance correction reduces distortion at low input amplitudes and demonstrates on the order of a 10-dB ACPR improvement compared to full-sample delay imbalance correction.

This article presents the methodology for designing triple-mode Doherty power amplifier (DPA) with multi-band operation and extended high efficiency range. It is illustrated that three different Doherty operation modes can be realized by simply re-setting the gate bias voltages while the DPA circuits keep unchanged. By employing a novel reciprocal gate bias DPA architecture, five operation bands have been achieved by the proposed DPA with larger than 9 dB high efficiency power range. The active load modulation process and theoretical performance of proposed DPA are analyzed in detail for each mode. For verification, a commercial GaN transistors-based DPA is designed and implemented with 1.76–1.96 GHz band in Mode I, 1.13–1.20/2.48–2.58 GHz bands in Mode II and 0.7–0.76/2.34–2.40 GHz bands in Mode III. The fabricated DPA achieves 7.0–10.5 dB saturation gain, 44.18–46.86 dBm peak output power and 41.9%–61.5% back-off efficiency. When stimulated by a 10 MHz long term evolution (LTE) modulation signal with 8.6 dB peaking-to-average ratio (PAPR), the adjacent channel power ratio (ACPR) of the fabricated DPA is better than −45 dBc after digital pre-distortion at 0.73, 1.18 and 1.85 GHz.

In this article, we propose the wideband digital predistortion (WDPD) for a highly linear and efficient GaN HEMT Doherty power amplifier (DPA). The WDPD is composed of the memory less DPD and the memory system, which compensates for the memory effects to achieve a highly linear wideband performance. The 11th‐memoryless polynomial characterizes the behavioral model of the DPA. The AM/AM and AM/PM lookup tables and the coefficients of the memory system are determined by the Recursive Least Square algorithm. For a 2‐FA WCDMA signal with 10 MHz carrier spacing at 2.14 GHz, the adjacent channel leakage ratio at ±10 MHz offset are improved over −50 dBc without the efficiency degradation at an output power of 36 dBm. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 484–487, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24951