A Novel Digital Feedback Predistortion Technique with Memory Lookup Table

We have developed a new adaptive digital predistortion (DPD) linearization technique based on analog feedback predistortion (FBPD). The lookup-table-based feedback input can remove the bandwidth limitation of the feedback circuit related to the loop delay, and suppress feedback oscillation by accurate digital control of the feedback signal. Moreover, the predistortion (PD) signal can be extracted very efficiently. By combining the feedback linearization and DPD linearization techniques, the performance of the predistorter is enhanced significantly compared to the conventional DPD. To clearly visualize the characteristics of digital FBPD (DFBPD), we have compared it to the conventional DPD based on the recursive least square algorithm using Matlab simulation. The results clearly show that the new method is a good linearization algorithm, better than a conventional DPD. For the demonstration, a Doherty power amplifier with 180-W peak envelope power is linearized using the proposed DFBPD. For a 2.14-GHz forward-link wideband code-division multiple-access signal, the adjacent channel leakage ratio at 2.5-MHz offset is -58 dBc, which is improved by 15 dB at an average output power of 43 dBm

This paper presents a multi lookup table (LUT) implementation scheme for the 3D distributed memory polynomial (3D-DMP) behavioral model used in Digital Predistortion (DPD) linearization for concurrent dual-band envelope tracking (ET) power amplifiers (PAs). The proposed 3D-Distributed Memory LUTs (3D-DML) architecture is suitable for efficient FPGA implementation. In order to optimize the linearization performance as well as to reduce the number of resources of the 3D-DML model, a new variant of the Orthogonal Matching Pursuit (OMP) algorithm is proposed to properly select the best LUTs. Experimental results show that the proposed strategy reduces the number of LUTs (i.e. the number of coefficients) while meeting the targeted linearity levels.

A new lookup-table linearization technique is developed based on the digital feedback and digital feedback/predistortion (DFBPD) concepts. The linearization characteristics are investigated through system simulation of a real power-amplifier model with 90-W peak envelope power. The DFB suppresses forward-path nonlinear distortion as a gain reduction due to the FB effect, and this technique enhances the system tolerance without any bandwidth limitation. As the PD network is added to the FB loop, the linearization performance and system tolerance are further improved because of more accurate PD signal extraction. In addition, the gain is purely determined by the FB path, so the gain fluctuation in the forward path, including amplifier aging and temperature effects, is suppressed. The analysis and simulation allow experimental evaluation of the linearization mechanism and performance of the DFBPD technique for an 802.16 e mobile Worldwide Interoperability for microwave access signal.

In this article, we study digital predistortion (DPD)-based linearization with a specific focus on millimeter-wave (mmW) active antenna arrays. Due to the very large-channel bandwidths and beam-dependence of nonlinear distortion in such systems, we present a closed-loop DPD learning architecture, lookup table (LUT)-based memory DPD models, and low-complexity sign-based estimation algorithms such that even continuous DPD learning could be technically feasible. To this end, three different learning algorithms-sign, signed regressor, and sign-sign-are formulated for the LUT-based DPD models such that the potential rank deficiencies, experienced in earlier methods, are avoided while facilitating greatly reduced learning complexity. The injection-based LUT DPD structure is also shown to allow for low numbers and reduced dynamic range of the involved LUT entries. Extensive RF measurements utilizing a state-of-the-art mmW active antenna array system at 28 GHz are carried out and reported to validate the methods, incorporating very wide channel bandwidths of 400 and 800 MHz while pushing the array close to saturation. In addition, the processing and learning complexities of the considered techniques are analyzed, which, together with the measured linearization performance figures, allows to assess the complexity-performance tradeoffs of the proposed solutions. Overall, the results show that efficient mmW array linearization can be obtained through the proposed methods at very low complexity.

In this paper, we present the quantitative study of the effects of the selected most important transceiver imperfections on the performance of digital baseband pre-distortion linearizers. Starting from the power amplifier model identification based on the measured data captured using the low-cost software defined radio platform (USRP), we evaluate the performance in term of out-of-band signal emissions at the power amplifier output for the case of typical representative of signals envisaged for fifth generation (5G) of mobile communication systems — filtered OFDM. The results are presented for the values of imperfections (IQ imbalances, DC offset) swept within the range of values corresponding to simple, commercially available wireless front-ends. We highlight the fact that the front-end imperfections can significantly affect the influence of pre-distorters.

Two methods for reconfigurable transmitters using frequency multipliers in conjunction with digital predistortion linearizers are developed. One method utilizes a circuit topology that can be switched between a fundamental-mode in-phase combined amplifier, and a push-push frequency doubler using input phasing. Investigation to maximize output harmonics out of regular power amplifiers (PAs) was performed, and the implementation of the device was successful for the amplifier- and doubler-mode operation. To satisfy optimal load-line conditions for the operation in both modes, a bi-tuned output-combining technique is introduced as well. Measurement results indicate that the circuit is able to transmit 28 dBm of output power at 900 MHz in the amplifier mode, and 22 dBm at 1800 MHz in the doubler mode. In combination with predistortion linearization, the reconfigurable transmitter was shown to be capable of amplifying IS-95B code-division multiple-access (CDMA) signals with an adjacent-channel power ratio (ACPR) up to -58dBc/30kHz. The second suggested method utilizes a fundamental-frequency PA followed by a varactor multiplier that can be bypassed with an RF switch. A varactor-diode doubler with a saturated conversion loss of 1.3 dB was built and tested. Using predistortion linearization techniques on both the PA and doubler, an ACPR of -53dBc/30kHz at 885-kHz offset was achieved for a CDMA signal transmitted at 1850 MHz.

A digital pre-distortion (DPD) scheme based on an adaptive-memory-length look-up table (AML-LUT) is proposed and experimentally demonstrated in a four-level pulse amplitude modulation (4-PAM) underwater optical wireless communication (UOWC) system. By implementing adaptive memory length for each pattern in the AML-LUT-based DPD, the size of the AML-LUT can be significantly reduced without sacrificing performance compared to both the full-size LUT and the multi-symbol simplified look-up table (MSS-LUT)-based DPDs. The performance of the proposed AML-LUT-based DPD is experimentally evaluated for a 625 Mbit/s 4-PAM UOWC over 1 m transmission length. Experimental results show that compared with the full-size LUT with a memory length of 7 (LUT-7)-based DPD, the proposed AML-LUT-based DPD (i) incurs a marginal power penalty of 0.5 dB at both the 7% hard-decision forward error correction (HD-FEC) and KP4-FEC threshold limits, while simultaneously reducing the implementation complexity (i.e., the LUT size) by 93%; (ii) achieves comparable transmission performance compared to the MSS-LUT-based DPD, while reducing the implementation complexity by 89%; and (iii) shows great potential for high-speed, low-complexity and memory-efficient intensity modulation and direct detection (IM/DD) UOWC and short-reach optical interconnects.

This brief presents a new variant of the orthogonal matching pursuit (OMP) algorithm for reducing the computational complexity of the digital predistortion (DPD) behavioral model in the forward path. The proposed spectral weighting OMP (SW-OMP) algorithm focuses on selecting the most relevant basis functions to compensate for the out-of-band residual distortion which may eventually be masked by the dominant in-band residual error. This basis selection is carried out in an off-line process that does not affect the computational complexity of the real-time closed-loop DPD but, on the contrary, reduces its complexity while enhancing the robustness. Experimental results show that by selecting the DPD coefficients with the SW-OMP, the inherent ACLR and NMSE degradation suffered when reducing the number of coefficients is mitigated under strong nonlinear operation, when compared to using the basis functions selected by the classical OMP algorithm.

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

This paper evaluates the effect of the phase shift between the two control signals in a dual-input load modulated
\nbalanced amplifier (LMBA). While the drain efficiency of the LMBA is not significantly affected by the phase shift between the control signals, the LMBA linearity instead can be significantly degraded if the phase shift parameter is not properly chosen. Therefore, we can predict the optimal phase shift between both LMBA control signals to enhance linearity levels when considering a 20 MHz bandwidth LTE transmission over a center frequency of operation ranging from 1.8 GHZ to 2.5 GHz. Experimental results showing the LBMA linearity and
\npower efficiency after digital predistortion (DPD) linearization
\nare presented. Finally, additional key parameters contributing
\nto improve the LBMA power efficiency are discussed.

ABSTRACTPower amplifiers (PAs) in mobile handsets are sensitive to changes in antenna impedance, thus suffering from load mismatch and generating complicated nonlinear distortion frequently. To solve this issue, a complexity‐reduced time domain poly‐harmonic distortion (CR‐TD‐PHD) model is proposed for the digital predistortion (DPD) linearization of handset PAs with load mismatch. By implementing a set of modified dual‐input magnitude‐selective affine (MSA) functions, the proposed CR‐TD‐PHD model can describe the inter‐modulation terms of the input signal and reflection signal accurately while avoiding the use of high‐order polynomial functions. Experimental tests are carried out on a load‐mismatched PA with a 100‐MHz 5G NR signal, and the results demonstrate that the proposed CR‐TD‐PHD model not only successfully reduces the complexity but also retains high linearization accuracy.

While polar modulation is a transmitter technique that is known to maximize energy efficiency, it also has no circuit linearity and traditionally is unable to produce signals that contain envelope zeros such as QAM and LTE. This polar transmitter solves this weakness and is modulation agnostic across the decade-wide tuning bandwidth of 200–2500 MHz. In particular, a conventional Nyquist filtered 256QAM signal is generated with error vector magnitude (EVM) less than 1.5% across the frequency range, and is below 1% across the bottom decade of frequency — without use of digital predistortion (DPD) linearization. Peak output power is 2.5 watts.

In this letter, we demonstrate a microwave Doherty amplifier employing an input signal envelope tracking technique. In the amplifier, the gate bias of the peaking amplifier is controlled according to the magnitude of the envelope. A 2.14-GHz Doherty amplifier is implemented using 4-W PEP LDMOSFETs, and an adaptive controlled gate bias circuit is constructed and the control shape is optimized experimentally. The performance of the microwave Doherty amplifier is compared with that of a class AB amplifier using one-tone, two-tone, and forward-link wideband code-division multiple access (WCDMA) signals. For a forward-link WCDMA signal, the measured power added efficiency (PAE) of the microwave Doherty amplifier is 39.4% at -30 dBc adjacent channel leakage ratio (ACLR), while that of the comparable class AB amplifier is 24.2% at the same ACLR level.

In this paper, a low-cost hardware implementation of a Look-up-Table(LUT) based digital predistorter (DPD) using Field Programmable Gate Array(FPGA) for power amplifier linearization is proposed. The LUT predistoter is implemented in Altera Stratix II DSP Development Board to simulate the inverse model for memoryless wide-band RF power amplifiers. The parameters of the LUT predistoter are identified using a dynamic exponential weighted moving average algorithm. This paper chooses the suitable table which is occupying less hardware resources from different tables by changing address width and word length for optimizing the design of LUT. Linearization performance is tested with a two-carrier wideband Wideband Code Division Multiple Access (WCDMA) signal.

This paper deals with Field Programmable Gate Array (FPGA) implementation design of a Predistorter real-time processing. The corresponding Baseband Digital Predistortion (DPD) is based on Memory Polynomial (MP) modelling of a UHF 8 MHz LDMOS Power Amplifier (PA). The PA MP model coefficients are estimated based on Least Square Estimation (LSE) algorithm. The proposed DPD design is using Look Up Table (LUT) for the Predistorter unit and the Indirect Learning Architecture (ILA) approach for estimating the coefficients of the predistorter. Implementation test results for the UHF LDMOS PA with DVB-T modulated signals showed good linearization performances with the adjacent channel power ratio (ACPR) reaching −46 dB.