Influence of transceiver imperfections to digital pre-distortion linearization — Application to 5G waveforms

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

Two methods for reconfigurable transmitters using frequency multipliers in conjunction with digital predistortion linearizers are developed. One method utilizes a circuit topology that can be switched between a fundamental-mode in-phase combined amplifier, and a push-push frequency doubler using input phasing. Investigation to maximize output harmonics out of regular power amplifiers (PAs) was performed, and the implementation of the device was successful for the amplifier- and doubler-mode operation. To satisfy optimal load-line conditions for the operation in both modes, a bi-tuned output-combining technique is introduced as well. Measurement results indicate that the circuit is able to transmit 28 dBm of output power at 900 MHz in the amplifier mode, and 22 dBm at 1800 MHz in the doubler mode. In combination with predistortion linearization, the reconfigurable transmitter was shown to be capable of amplifying IS-95B code-division multiple-access (CDMA) signals with an adjacent-channel power ratio (ACPR) up to -58dBc/30kHz. The second suggested method utilizes a fundamental-frequency PA followed by a varactor multiplier that can be bypassed with an RF switch. A varactor-diode doubler with a saturated conversion loss of 1.3 dB was built and tested. Using predistortion linearization techniques on both the PA and doubler, an ACPR of -53dBc/30kHz at 885-kHz offset was achieved for a CDMA signal transmitted at 1850 MHz.

We have developed a new adaptive digital predistortion (DPD) linearization technique based on analog feedback predistortion (FBPD). The lookup-table-based feedback input can remove the bandwidth limitation of the feedback circuit related to the loop delay, and suppress feedback oscillation by accurate digital control of the feedback signal. Moreover, the predistortion (PD) signal can be extracted very efficiently. By combining the feedback linearization and DPD linearization techniques, the performance of the predistorter is enhanced significantly compared to the conventional DPD. To clearly visualize the characteristics of digital FBPD (DFBPD), we have compared it to the conventional DPD based on the recursive least square algorithm using Matlab simulation. The results clearly show that the new method is a good linearization algorithm, better than a conventional DPD. For the demonstration, a Doherty power amplifier with 180-W peak envelope power is linearized using the proposed DFBPD. For a 2.14-GHz forward-link wideband code-division multiple-access signal, the adjacent channel leakage ratio at 2.5-MHz offset is -58 dBc, which is improved by 15 dB at an average output power of 43 dBm

This paper presents a multi lookup table (LUT) implementation scheme for the 3D distributed memory polynomial (3D-DMP) behavioral model used in Digital Predistortion (DPD) linearization for concurrent dual-band envelope tracking (ET) power amplifiers (PAs). The proposed 3D-Distributed Memory LUTs (3D-DML) architecture is suitable for efficient FPGA implementation. In order to optimize the linearization performance as well as to reduce the number of resources of the 3D-DML model, a new variant of the Orthogonal Matching Pursuit (OMP) algorithm is proposed to properly select the best LUTs. Experimental results show that the proposed strategy reduces the number of LUTs (i.e. the number of coefficients) while meeting the targeted linearity levels.

Design of high-efficiency power amplifier (PA) is one of the key challenges to realize green radios, wherein digital predistortion (DPD) is deployed to reduce the PA’s power back-off and thus increase its power efficiency. As the bandwidth of the transmit signal increases, stringent requirements are posed on the DPD linearization performance with limited sampling rate and dynamic range for the analog-to-digital converter (ADC) in the DPD feedback channel. In this paper, under a fixed ADC sampling rate, novel DPD architecture is proposed to compensate for the PA nonlinearity with limited ADC dynamic range. In the feedback channel of the proposed architecture, an extra radio frequency (RF) cancellation chain is introduced to eliminate the linear component of the PA amplified signal, and thus the requirement on the ADC dynamic range can be significantly reduced. Subsequently, by accurately estimating the loop delay and attenuation of the cancellation chain, the baseband replica of the RF cancelling signal is recovered, and the original PA output signal is rebuilt to estimate the DPD coefficients. Finally, experiments show that for the long term evolution (LTE)-advanced signals, the proposed architecture can achieve an adjacent channel leakage ratio lower than −47.6 dBc, which outperforms the conventional DPD by about 3.4 dB, with the effective bits of the ADC being reduced by 4.4 and a power added efficiency of 43.8% with 7.3 dB power back-off being observed for a fabricated Doherty PA with 50-dBm saturation power.

Digital predistortion (DPD) is a cost-effective method to linearize power amplifiers (PAs) in modern wireless transceivers. In block-based predistortion, which is a two-step process involving DPD identification and linearization, the linearization performance is related to the PA output power during identification. In this brief, we investigate this relation and find the optimum PA output power in the identification for the best linearization performance. A scaling factor is applied to the input signal to control the PA output power during the identification. Since the optimum PA output power for the identification is expected to depend on the probability density function (pdf) of the input signal magnitude and the PA response, we choose signals with different pdfs and a PA with different linearity settings for our study. The factors that affect the linearization performance are identified and we explain how they lead to different linearization performances for different PA responses and pdfs of the input signal magnitude. Measurements using a PA that operates at 900 MHz with two different Universal Mobile Telecommunications System signals were carried out. The linearization performance is quantified as the mean squared error (MSE) between the input and output signals. Depending on the pdf of the input signal magnitude, we found MSE improvements between 2 and 10 dB if the optimum PA output power is chosen during the identification.

The application of digital predistortion in base band signal is an extended method of amplifier linearization to reduce the adjacent channel interference (ACI) in those systems in which a varying envelope modulation scheme like OFDM and MQAM is used. Digital baseband predistortion is a highly cost-effective way to linearize power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored. In this paper we proposed a new technique for adaptation of digital predistorter that considers memory effects in power amplifiers. This method is a combination of two techniques, memory polynomial predistortion and slope-dependent method. This new technique is validated by using a 1.9 GHz 60W LDMOS power amplifier and various signals such as 2-carrier and 3-carrier CDMA.

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

A novel approach for power amplifier (PA) characterization suitable for single iteration digital predistorter synthesis is proposed. This approach consists of synergetic crest factor reduction and baseband digital predistortion to avoid the average power variation at the input of the PA between the characterization and linearization steps. This is achieved by bypassing the crest factor reduction block during the characterization step and by applying it concurrently with digital predistortion in the linearization step. First, the PA's behavior sensitivity to the average input power is evaluated. The limitations of conventional approaches for the PA characterization, in the context of single iteration digital predistortion, are then demonstrated. The performance of the proposed technique is validated experimentally on a 300-W peak PA. The measured improvement of the adjacent channel power ratio at the output of the linearized amplifier is 16 dBc for the conventional approach and 29 dBc for the proposed approach.

This paper investigates the trade-off between power amplifier (PA) nonlinearity, output power backoff (OBO), digital predistortion (DPD), and clipping and filtering (CF) in terms of energy consumption. The energy efficiency of a PA depends on the OBO of the signal and usually increases as the OBO decreases. Peak to average power ratio (PAPR) reduction methods like CF and PA linearization algorithms like DPD methods allow the use of a smaller OBO. Those algorithms show best results when used together. By studying the trade-off between the power consumed in the CF and DPD circuits versus having a larger OBO for a target bit-error rate (BER), we show that below a certain PA output power the power consumption is not reduced by decreasing the OBO. We also show that the increase in distortion noise when using DPD and CF might defeat the purpose of their use in terms of power consumption. Given the trend toward smaller cells like femtocells, requiring less output power, CF and DPD may not be required at all, leading to a simpler and power saving transmitter design.

We consider digital predistortion (DPD) for linearizing power amplifiers (PAs) of hybrid MIMO systems with subarrays. Designing such a DPD scheme is difficult because one DPD should linearize all PAs of a subarray whose beamforming coefficients are time-varying. We develop an adaptive DPD technique for each subarray based on direct learning method minimizing the sum of squared errors between the input and output signals of PAs. Use of the least mean square (LMS) Newton algorithm is proposed to adaptively control the DPD parameters. It is shown that the proposed DPD can simultaneously linearize multiple PAs in a subarray irrespective of its beamforming coefficients. Computer simulation results demonstrate that the proposed scheme can perform better than an alternative scheme that designs the DPD based on one of the PA outputs and uses the resulting DPD for all PAs of the subarray.

This paper evaluates the effect of the phase shift between the two control signals in a dual-input load modulated
\nbalanced amplifier (LMBA). While the drain efficiency of the LMBA is not significantly affected by the phase shift between the control signals, the LMBA linearity instead can be significantly degraded if the phase shift parameter is not properly chosen. Therefore, we can predict the optimal phase shift between both LMBA control signals to enhance linearity levels when considering a 20 MHz bandwidth LTE transmission over a center frequency of operation ranging from 1.8 GHZ to 2.5 GHz. Experimental results showing the LBMA linearity and
\npower efficiency after digital predistortion (DPD) linearization
\nare presented. Finally, additional key parameters contributing
\nto improve the LBMA power efficiency are discussed.

ABSTRACTPower amplifiers (PAs) in mobile handsets are sensitive to changes in antenna impedance, thus suffering from load mismatch and generating complicated nonlinear distortion frequently. To solve this issue, a complexity‐reduced time domain poly‐harmonic distortion (CR‐TD‐PHD) model is proposed for the digital predistortion (DPD) linearization of handset PAs with load mismatch. By implementing a set of modified dual‐input magnitude‐selective affine (MSA) functions, the proposed CR‐TD‐PHD model can describe the inter‐modulation terms of the input signal and reflection signal accurately while avoiding the use of high‐order polynomial functions. Experimental tests are carried out on a load‐mismatched PA with a 100‐MHz 5G NR signal, and the results demonstrate that the proposed CR‐TD‐PHD model not only successfully reduces the complexity but also retains high linearization accuracy.

This brief presents a new variant of the orthogonal matching pursuit (OMP) algorithm for reducing the computational complexity of the digital predistortion (DPD) behavioral model in the forward path. The proposed spectral weighting OMP (SW-OMP) algorithm focuses on selecting the most relevant basis functions to compensate for the out-of-band residual distortion which may eventually be masked by the dominant in-band residual error. This basis selection is carried out in an off-line process that does not affect the computational complexity of the real-time closed-loop DPD but, on the contrary, reduces its complexity while enhancing the robustness. Experimental results show that by selecting the DPD coefficients with the SW-OMP, the inherent ACLR and NMSE degradation suffered when reducing the number of coefficients is mitigated under strong nonlinear operation, when compared to using the basis functions selected by the classical OMP algorithm.

The inherent nonlinear behavior exhibited by power amplifiers (PAs) in saturation mode is a major impediment in wireless systems to achieve higher power efficiency, and higher spectral efficiency. Although PA behavioral modeling and digital predistortion (DPD) techniques are widely utilized at transmitter to characterize and linearize such distorted nonlinear output of PAs, the nonlinear distortions with memory effects have become more severe due to simultaneous strong crosstalk between multiple PA branches in multiple-input multiple-output (MIMO) arrays. Furthermore, current multi-input behavioral models suffer from a sharp increase in number of coefficients as the number of transmitter path increases in MIMO. In overcoming these challenges, we propose a decomposed cross-correlation based single-input-single-output (CC-SISO) behavioral modeling architecture. The proposed solution utilizes a low-cost, novel cross-correlation based method to estimate and cancel the simultaneous nonlinear and reverse crosstalk from multiple PA branches. Once the crosstalk is mitigated, the MIMO DPD can be implemented with single-input DPD blocks which significantly reduces the complexity. Furthermore, CC-SISO DPD eliminates the requirement for signal feedback paths before and after the PA, and thus reduces overall hardware implementation complexity. Through simulations, we demonstrate that the proposed CC-SISO architecture can reduce the overall complexity of state-of-art multi-input DPD models for MIMO systems.