Adaptive multichannel decision feedback equalization using subarray processing

We proposed an adaptive two-stage nonlinear feedforward equalizer and decision feedback equalizer to minimize the negative influence of nonlinear distortions. A data rate of 960 Mbit/s is experimentally achieved on the guided visible-light transparent transmission over a 100-m ultra-large effective area pure silica fiber. The experimental results verified the effectiveness and improvement of the proposed method compared with the traditional feedforward post-equalizers.

A 10 Gb/s adaptive analog decision feedback equalizer (DFE) with 6 taps is realized in 0.13 μm CMOS. A modified Cherry-Hooper stage is designed as the delay element in the feed-forward path. An analog implementation of the LMS algorithm is used to continuously adapt the feedback filter coefficients. A clock and data recovery (CDR) circuit is used to extract the clock from the DFE output. The adaptive DFE dissipates 452 mW and can equalize PRBS data corrupted by a 300m-long multimode fiber (MMF) achieving BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> .

A novel PAM4 receiver with adaptive threshold voltage, adaptive decision feedback equalizer and fixed linear equalizer has been presented. The proposed techniques enable threshold voltage to be adjusted automatically depending on data rate, signal swing and loss of channel. Consequently the receiver can be used in various situations without being manually calibrated. Adaptive decision feedback equalizer for PAM4 signaling is proposed, incorporated with sign-sign least mean square algorithm. Simulation results across lossy channel show proper convergence of threshold voltage and decision feedback equalizer values with the proposed receiver.

This paper presents a 6.25Gb/s adaptive decision feedback equalizer (DFE) for high speed backplane communication, which consists of a high-speed DFE and an adaptation engine based on Sign-Sign LMS algorithm. Half-rate structure and current mode logic are employed to pursue a high operating speed. The adaptation engine is composed of sense amplifiers (SA), a 5-bit up/down counter and a 5-bit DAC, which are implemented in CMOS logic at 781.25MHz. Designed in 0.18µm CMOS process, the equalizer has an area of 0.6×0.55mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including I/O pads, and the static power consumption is 45.9mW under 1.8V power supply. Measurement results show that the proposed equalizer can adapt to signals achieved from PCB channels of different lengths, and the data rate can be up to 6.8Gb/s with horizontal eye opening of outputs larger than 0.8UI.

This brief presents a 1.62-to-10-Gb/s receiver for next generation video interconnected with an adaptive decision-feedback equalizer (DFE). The adaptive DFE facilitates the best bit error rate (BER) performance for various losses of video cables. A differential-pair stage is added to the DFE for extending an effective DFE range, presetting a minimum data level, and calibrating a mismatch offset. Circuit techniques are proposed to relax timing constraints for the direct-feedback DFE architecture. A referenceless frequency acquisition is performed during a dedicated clock recovery phase. The measured BER at 10 Gb/s is lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> with a 23-dB loss cable. The RMS jitter and the peak-to-peak jitter of a recovered clock are measured as 2.38 ps and 17.5 ps, respectively. The prototype chip is implemented in 65-nm CMOS technology and occupies an active area of 0.254 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . This receiver consumes 24.4 mW at 10 Gb/s, corresponding to the energy efficiency of 2.44 pJ/b, which is the lowest compared to other recently published video interface receivers.

SUMMARYThis paper proposes a novel adaptive decision feedback equalizer (DFE) based on compact self‐constructing recurrent fuzzy neural network (CSRFNN) for quadrature amplitude modulation systems. Without the prior knowledge of channel characteristics, a novel training scheme containing both compact self‐constructing learning (CSL) and real‐time recurrent learning algorithms is derived for the CSRFNN. The proposed CSL algorithm adopts two evaluation criteria to intelligently decide the number of fuzzy rules that are necessary. The real‐time recurrent learning is performed simultaneously with the CSL at each time instant to adjust DFE parameters. The proposed DFE is compared with several neural network‐based DFEs on a nonlinear complex‐valued channel. The results show that the CSRFNN DFE is superior to classical neural network DFEs in terms of symbol‐error rate, convergence speed, and time cost. Copyright © 2011 John Wiley &amp; Sons, Ltd.

In a TDMA mobile communication system, an adaptive decision feedback equalizer (DFE) is the common device to compensate the intersymbol interference caused by the multipath effect. Due to the fast fading characteristic of channels, most conventional DFEs use the recursive least square (RLS) algorithm. However, it is known that the RLS algorithm is computationally intensive and not easy to implement. The LMS is well known for its simple structure, however, due to its poor tracking property, it cannot be used. Recently, a multiple-training and multiple-tracking LMS (MTT-LMS) algorithm was developed. It was shown that the DFE trained by the MTT-LMS algorithm can yield a satisfactory result at moderate mobile speed. The MTT-LMS algorithm retains the simple structure of the LMS algorithm and is suitable for hardware implementation. In this paper, we consider the ASIC design of the MTT-LMS DFE for application to North American IS-54 systems. We have designed an efficient architecture which not only has small chip area but low clock rate. We also develop a new decision device to provide the desired signal for the MTT-LMS algorithm and the implementation of the device is simpler than the conventional one.

A parallel adaptive decision feedback equalizer (ADFE) architecture is proposed. It allows adaptation at every sample to effectively equalize intersymbol interference for applications that operate at high sampling rates and require fast tracking capability. It is shown that if the effect of error propagation is small, the filter coefficients of the parallel ADFE will be exactly the same as those of a serially adapting ADFE. Simulation confirms that the parallel ADFE effectively tracks a time-varying channel with typical signal-to-noise ratios at a sampling rate four times higher than that of a serial ADFE, while under the same channel condition a previously proposed block ADFE fails to converge and becomes unstable.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Optical wireless communication (OWC) systems use the atmosphere as a propagation medium. However, a common problem is that from time to time moderate cloud and fog emerge between the receiver and the transmitter. These adverse weather conditions impose temporal broadening and power loss on the optical signal, which reduces the digital signal-to-noise ratio (DSNR), produces significant intersymbol interference (ISI), and degrades the communication system's bit error rate (BER) and throughput. We propose and investigate the use of a combined adaptive bandwidth mechanism and decision feedback equalizer (DFE) to mitigate these atmospheric multipath effects. Based on theoretical analysis and simulations of DSNR penalties, BER, and optimum system bandwidths, we show that a DFE improves the outdoor OWC system immunity to ISI in foggy weather while maintaining high throughput and desired low BER.

A 10Gb/s half-rate adaptive 1-tap speculative decision feedback equalizer (DFE) is implemented in 65nm CMOS. Adaption of the DFE is achieved by using a novel mixed-signal implementation of the sign-sign least mean square (SS-LMS) algorithm to continuously adapt the coefficient of the unique tap. The simulation results show that the DFE can totally compensate 16.2dB loss at the Nyquist frequency for 10Gb/s PRBS31 transmission over 700mm RLGC (resistance, inductance, conductance and capacitance) channel. The active layout area is 0.01 mm2 and total power consumption is 24mW for 1.2V supply.

A 10 Gbit/s serial link receiver with an offset-calibrated continuous-time linear equaliser, an adaptive one-tap half-rate speculative decision feedback equaliser (DFE) and a phase-interpolator-based clock and data recovery is presented. Adaption of the DFE is achieved by using a novel mixed-signal implementation of the sign-sign least mean square algorithm to save the cost of hardware and power. Fabricated in 65 nm CMOS technology, the receiver can totally compensate 24.85 dB channel loss at a bit error rate of 10−12. The active chip area is 0.08 mm2 and the total power consumption is 57 mW from a 1.2 V supply.

Among existing works of high-speed pipelined adaptive decision feedback equalizer (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving than the parallel processing or Look-ahead approaches. However, it suffers from both the signal-to-noise ratio (SNR) degradation and slow convergence rate. In this paper, we employ the predictive parallel branch slicer (PPBS) to eliminate the dependencies of the present and past decisions so as to reduce the iteration bound of decision feedback loop of the ADFE. By adding negligible hardware complexity overheads, the proposed architecture can help to improve the output mean-square error (MSE) of the ADFE compared with the Relaxed Look-ahead ADFE architecture. Moreover, we show the superior performance of the proposed pipelined ADFE by using theoretical derivations and computer simulation results. A VLSI design example using Avant! 0.35-/spl mu/m CMOS standard cell library is also illustrated. From the post-layout simulation results, we can see that the PPBS scheme requires only 38.4% gate count overhead, but it can help to reduce the critical path from 7.06 to 4.69 ns so as to meet very high-speed data transmission systems.

For PC DRAM buses, the number of slots per channel has decreased as data rates have increased. This limits the maximum memory capacity per channel. Signal equalization can be used to increase bit-rates for channels with a large number of slots and offer a cost effective method to solve the memory capacity problem. This paper presents a blind adaptive decision feedback equalizer (DFE) that enables high data-rates with a large number of slots per channel. Measurements at 2.6 Gb/s over a four-drop bus are presented.

In this work we present a per-subchannel nonlinear adaptive equalizer for a class of filter bank based multicarrier (FBMC) systems. We consider the class of exponentially modulated FBMCs with offset quadrature amplitude modulated (OQAM) input symbols. We present a fractionally spaced adaptive decision feedback equalizer (DFE) based on the least-mean-square (LMS) algorithm. The input of each equalizer comprises only the output of each subchannel. In the simulation results we show that, despite its increased computational complexity, the performance and higher bandwidth efficiency of OQAM FBMC systems makes them a competitive alternative to conventional multicarrier systems like cyclic prefix based orthogonal frequency division multiplexing (CP-OFDM).

SUMMARYIn this paper, an adaptive modulation scheme for the multiple‐input multiple‐output (MIMO) frequency‐selective channels is investigated. We consider a scenario with precoded block‐based transceivers over spatially correlated Rayleigh multipath MIMO channels. To eliminate the inter‐block interference, the zero‐padding is used. The receiver is equipped with a MIMO minimum‐mean‐squared‐error decision feedback equalizer. The precoder aims to force each subchannel to have an identical signal‐to‐interference‐plus‐noise ratio (SINR). To adjust the constellation size, the unbiased mean square error at the equalizer output is sent back to the transmitter. To simplify our analysis, the feedback channel is considered as instantaneous and error free. We first derive the probability density function of the overall SINR for flat fading and frequency‐selective channels. On the basis of the probability density function of the upper bound of the SINR, we evaluate the system performance. We present accurate closed‐form expressions of the average spectral efficiency, the average bit error rate and the outage probability. The derived expressions are compared with Monte Carlo simulation results. Furthermore, we analyze the effect of the channel spatial correlation. Copyright © 2013 John Wiley &amp; Sons, Ltd.