AI-Powered Real-Time Inspection for Electronic Component Assembly

Application of numerical analysis to the optimisation of electronic component reliability screening and assembly processes

This paper introduces a pioneering method for real-time image processing in electronic component assembly, revolutionizing quality control in manufacturing. By promptly capturing images from pick-and-place machines during the interval between component pick-up and mounting, defects are identified and promptly addressed in line. This proactive approach ensures that defective components are rejected before mounting, effectively preventing issues from ever occurring, thus significantly enhancing efficiency and reliability. Leveraging rapid network protocols such as gRPC and orchestration via Kubernetes, in conjunction with C++ programming and TensorFlow, this approach achieves an impressive average turnaround time of less than 5 milli-seconds. Rigorously tested on 20 operational production machines, it not only ensures adherence to IPC-A-610 and IPC-STD-J-001 standards but also optimizes production efficiency and reliability.

Fluxing underfill materials are widely used in electronics manufacturing to improve reliability performance. The prevailing process of applying fluxing underfill is by dispensing the desired volume onto the printed circuit board with optimized patterns. The underfill cure is accomplished concurrently with solder joint formation in the reflow process. Even though the processing time of applying underfill material by this method is much shorter than that of the conventional capillary flow underfill process, the processing time of underfill dispensing is much longer than other process steps (e.g., printing, chip placement, reflow, etc). The current underfill dispensing process is a bottleneck in the high-speed electronic assembly manufacturing. Besides the long processing time, the underfill dispensing process requires complicated and expensive dispensing machines, which increase the manufacturing cost. In this research, an innovative dispenseless fluxing underfill process and the associated module have been developed to achieve high-speed SMT compatible underfill processing. The underfill application and chip placement are integrated into one process step that is accomplished by one placement machine. The prototyping of flip chip on board assemblies utilizing this innovative process shows dramatically reduced processing time. It also improves the reliability of electronic assembly systems. This invention enables remarkable cost savings from shortening processing time and eliminating the capital cost associated with underfill dispensing machines. The proposed process and module are fully compatible with the current SMT electronic manufacturing infrastructure. The dispenseless underfill process provides a high-speed and cost-effective solution for flip chip, CSP, and BGA electronic packaging assembly.

The rapid growth of modern technology place greater demand on electronic products’ performance and quality. As for the printed circuit board (PCB) assembly of electronic components through surface mounting technology (SMT), high-pixel charge coupled device (CCD) can only screen local images during image collection because of its limited vision. A rapid image mosaic technology has been proposed to seamlessly stitch the local images with overlapping boundaries. The complete image of PCB assembly has been acquired through rapid area matching method within double Mark points and Mark circle. The experiment results show that this method can greatly reduce the image-mosaic time and fairly improve the real-time performance of modern automatic optical inspection (AOI) equipment. Furthermore, such method avoids the alignment error from the characteristic points for noise jamming or noise shielding, and therefore obtains better robustness.

Chapter 4 - Fabrication methods of miniaturized analysis

Interest in Lead-free solder alloys is rapidly increasing in the electronics industry. Contemplating a move away from the large existing knowledge base on assembly with Sn/Pb solder raises many concerns. These may be classified into five areas: Solder Alloys and Fluxes. Many alloys (some proprietary) have been identified as contenders. Unfortunately, it seems unlikely that any single alloy will become as dominant as Sn/Pb. Most alloys (if not all of them) will require new flux formulations. PCBs and Components PCB and Component suppliers will face difficult choices in removing Lead from their products while making them able to tolerate the higher reflow temperatures required by most Lead-free alloys. Assembly and Rework Processes Higher melting point alloys will affect every step of the electronics assembly process. Long Term Reliability The long-term reliability of the selected alloy(s) must be assessed for each application. Inspection and Quality Specifications These standards must be revised to reflect the different appearance and wetting properties of Lead-free alloys. This paper will detail some of the evaluations and testing that must be done to address these concerns. It will be of interest to process engineers, and electronic assembly managers interested in switching to lead-free assembly, as well as to design and environmental engineers seeking to have a better understanding of the implications of lead-free soldering on the overall assembly process.

The end of the cold war has resulted in many changes for the Nuclear Weapons Complex (NWC). We now work in a smaller complex, with reduced resources, a smaller stockpile, and no new phase 3 weapons development programs. This new environment demands that we re-evaluate the way we design and produce nuclear weapons. The Defense Program (DP) Business Practices Re-engineering activity was initiated to improve the design and production efficiency of the DP Sector. The activity had six goals: (1) to identify DP business practices that are exercised by the Product Realization Process (PRP); (2) to determine the impact (positive, negative, or none) of these practices on defined, prioritized customer criteria; (3) to identify business practices that are candidates for elimination or re-engineering; (4) to select two or three business practices for re-engineering; (5) to re-engineer the selected business practices; and (6) to exercise the re-engineered practices on three pilot development projects. Business practices include technical and well as administrative procedures that are exercised by the PRP. A QFD exercise was performed to address (1)-(4). The customer that identified, defined, and prioritized the criteria to rate the business practices was the Block Change Advisory Group. Five criteria were identified: cycle time, flexibility, cost, product performance/quality, and best practices. Forty-nine business practices were identified and rated per the criteria. From this analysis, the group made preliminary recommendations as to which practices would be addressed in the re-engineering activity. Sixteen practices will be addressed in the re-engineering activity. These practices will then be piloted on three projects: (1) the Electronic Component Assembly (ECA)/Radar Project, (2) the B61 Mod 11, and (3) Warhead Protection Program (WPP).

This study investigates the integration of reinforcement learning (RL) with optimal control to enhance precision and energy efficiency in industrial robotic manipulation. A novel framework is proposed, combining Deep Deterministic Policy Gradient (DDPG) with a Linear Quadratic Regulator (LQR) controller, specifically applied to the ABB IRB120, a six-degree-of-freedom (6-DOF) industrial manipulator, for pick-and-place tasks in warehouse automation. The methodology employs an actor–critic RL architecture with a 27-dimensional state input and a 6-dimensional joint action output. The RL agent was trained using MATLAB’s Reinforcement Learning Toolbox and integrated with ABB’s RobotStudio simulation environment via TCP/IP communication. LQR controllers were incorporated to optimize joint-space trajectory tracking, minimizing energy consumption while ensuring precise control. The novelty of this research lies in its synergistic combination of RL and LQR control, addressing energy efficiency and precision simultaneously—an area that has seen limited exploration in industrial robotics. Experimental validation across 100 diverse scenarios confirmed the framework’s effectiveness, achieving a mean positioning accuracy of 2.14 mm (a 28% improvement over traditional methods), a 92.5% success rate in pick-and-place tasks, and a 22.7% reduction in energy consumption. The system demonstrated stable convergence after 458 episodes and maintained a mean joint angle error of 4.30°, validating its robustness and efficiency. These findings highlight the potential of RL for broader industrial applications. The demonstrated accuracy and success rate suggest its applicability to complex tasks such as electronic component assembly, multi-step manufacturing, delicate material handling, precision coordination, and quality inspection tasks like automated visual inspection, surface defect detection, and dimensional verification. Successful implementation in such contexts requires addressing challenges including task complexity, computational efficiency, and adaptability to process variability, alongside ensuring safety, reliability, and seamless system integration. This research builds upon existing advancements in warehouse automation, inverse kinematics, and energy-efficient robotics, contributing to the development of adaptive and sustainable control strategies for industrial manipulators in automated environments.

This study investigates lignocellulose nanofibrils (LCNF) as a sustainable alternative material for printed circuit board (PCB) substrates, demonstrating an application through the development of an eco-friendly computer mouse demonstrator. LCNF is derived from lignin-rich cellulose pulp, a side stream product of biorefinery processes, combining the natural strength of cellulose fibrils with lignin to enhance mechanical and electrochemical properties. The research outlines the process of fibrillating lignin-rich cellulose pulp at 10 kW/h per kg into LCNF, followed by thermal and pressure treatment (at Δp = 50 – 1500 kN, ΔT = 30 – 120 °C) to achieve a rigid PCB substrate. Comprehensive characterization of the LCNF substrate included assessments of its mechanical properties (flexural and tensile testing), dimensional stability, electrical properties, surface uniformity and thermal conductivity. The LCNF PCB was integrated in a computer mouse demonstrator featuring inkjet printing of circuit layouts and electronic component assembly, while the mouse housing was designed and 3D-printed using eco-friendly Wood-PLA filament. Electrical properties characterization of the printed circuit and resulting functionality of the computer mouse showcases a sustainable approach to eco-electronics using wood-derived materials. This study underscores the potential of wood-derived nanomaterials like LCNF to reduce electronic waste (e-waste) associated with conventional PCB materials and promote the development of a more eco-friendly electronics, contributing to sustainable, high-performance ecoPCBs and advancing green technology.

We present a novel, wafer-based fabrication process that enables integration and assembly of electronic components, such as ASICs and decoupling capacitors, with flexible interconnects. The electronic components are fabricated in, or placed on precisely defined and closely-spaced silicon islands that are connected by interconnects embedded in parylene-based flexible thin film. This fully CMOS compatible approach uses optimized DRIE processes and an SiO2 mesh-shaped mask, allowing for the simultaneous definition of micrometer- to millimeter-sized structures without compromising the flexibility of the device. In a single fabrication flow a unique freedom in dimensions of both the flexible film and the silicon islands can be achieved making this new technique ideal for the realization of semi-flexible/foldable implantable devices, where structures of different sizes have to be combined together for the ultimate miniaturization.

Sanitary ceramic products, such as toilet and wash basin, are widely used in our daily life. Sanitary ceramics are expected to have some excellent physical properties, such as corrosion resistance, easy cleaning, and low water absorption. However, surface defects in sanitary ceramics are inevitable due to complex production processes and changing production environment. Therefore, surface defect detection must be performed in the manufacturing process of sanitary ceramics. There are many types of surface defects in sanitary ceramics, and different types of defects have large differences in characteristics and scales. Traditional detection methods with artificially designed features and classifiers are difficult to apply in this context. In addition, there are few studies on surface defect detection methods of sanitary ceramics based on deep neural networks. In this article, a lightweight real-time defect detection network based on the lightweight backbone MobileNetV3 is presented. The proposed network achieves multi-scale detection of surface defects in sanitary ceramics with a multi-layer feature pyramid. Combining region proposal network and anchor-free method, real-time defect detection is achieved. Finally, a detection head with channel attention structure and a low-level mixed feature classification strategy is used to perform defect classification with higher accuracy. Experimental results show that the proposed approach achieves at least 22.9% detection speed improvement and 35.0% average precision improvement while reducing memory consumption by at least 8.4% compared with the classic one-stage SSD, YOLO V3 and two-stage Faster R-CNN methods.

The purpose of this paper is to give the nonspecialist some tools he can use to gain insight into some of the complex thermal problems encountered in electronic assemblies. Some causes of thermal problems in electronic components and assemblies are briefly reviewed on a fundamental level. This review includes a discussion of some basic thermal parameters, the effect of the thermal environment on other physical parameters, and ways the thermal environment affects the operating characteristics and life of electronic assemblies. Most of the paper is devoted to specific thermal design and cooling problems. Techniques are presented which can be used to determine the thermal stresses that develop in some assemblies during soldering, shipping, and storage; and to determine the cyclic thermal stresses that develop during normal operation. In addition, some fundamentals of heat transfer from minute electronic components by conduction, convection, and radiation are reviewed, and techniques are described that can be used to predict the heat transfer from both single and multiple sources. Experimental and analytical studies are cited to illustrate each topic discussed. For example, experimental data are presented to show the effect temperature has on the coefficient of thermal expansion and the compliance of epoxy-glass composites and its effect on stress relaxation in solder, These data are then used to analyze the form of the stresses that exist in a plated-through hole during soldering and temperature cycling.

The worldwide movement towards lead-free (electroplated pure tin) electronic component lead finishes re-introduces a familiar problem to the high reliability electronics community, tin whiskers. This movement to eliminate lead from electronic assemblies is driven by legislation in the EU (WEEE and ROHs) and in Japan to eliminate lead from electronic products by 2006. While electroplated pure tin is a component surface finish that has existed in the electronics industry for decades, there is a well-known phenomenon related to pure tin plating, known as “tin whiskers”. Tin whiskers are conductive, pure tin crystals that spontaneously “grow” from an electroplated pure tin surface. The growth mechanism for whiskers is not well understood and can be characterized as unpredictable in many cases. Tin whiskers can bridge to near-by conductors causing a range of failures in critical systems. As the availability of high reliability electronic components with tin-lead terminations continues to shrink, high-reliability equipment manufacturers are being forced to use commercial products (COTS) in many applications. These are precisely the types of components targeted by the lead-free movement. More and more pure tin is finding it's way into high-reliability electronics. COTS components can be tested for performance and reliability using industry and government test methods. Unfortunately there is no accepted test method to determine if a component will exhibit tin whiskers in a specific application or environment. This has lead to a number of mitigation strategy initiatives in industry and various consortia investigating methods such as conformal coating, matte tin plating and hot solder dip. This paper will focus on the latter and the capabilities of current technology to efficiently and effectively replace lead-free electro plating with hot dipped solder.

Webinar organized by the SMTA Upper Midwest Chapter Technical Presentation: This one-hour presentation addresses a number of design challenges when developing and implementing high-density semiconductor packaging; 3D die-stacking, package-stacking as well as innovative system-in-package solutions. Companies requiring system level capability have successfully developed very complex system-on-chip semiconductors as well, but for a number of products needing to reach the market faster, some companies have selected alternative paths. Many have found that combining several mature die elements or adopting "~chicklet"™ components utilizing ultra-high-density interposers has actually proved superior to the multiple function die concepts because it minimizes risk, significantly reduces development time and cost. Topics covered: Array Package Evolution and Standards Semiconductor Die and Package Stacking Wafer and Panel Level 2.5D and 3D Packaging Ultra-High-Density Organic Interposer Design Material presented has been developed to better enable the product designer and manufacturing specialist to evaluate a broad number of semiconductor packaging methodologies. The examples shown will furnish both physical and monetary benefits gained using multiple die packaging. Intended audience: PCB Designers, Design Engineers and those responsible for semiconductor package and electronic product development, assembly processing and manufacturing. Biography: Vern Solberg is an independent engineer specializing in SMT and microelectronics design and manufacturing technology. He has served the industry for more than thirty years in areas related to both commercial and aerospace electronic products. Vern has acted as chairman and co-chair in developing the current IPC 7900 series standards, is a recipient of the IPC Presidents Award, the Raymond E. Pritchard Hall of Fame Award, a two-time recipient of the Surface Mount Technology Associations "Founders Award", He is also credited with several patents for multiple-die IC packaging innovations including the folded-flex 3D package technology. In addition to developing numerous technical papers and PCB designer focused magazine columns, Solberg is the author three books related to SMT design for manufacturing, the latest being "PCB Designers Handbook for Surface Mount and Microelectronics" Files Available to Download: Recorded Presentation (On-Demand)

Funded by the Singapore National Science and Technology Board (NSTB), CAMTech is collaborating with a Singaporean research institute and two industry partners with the objective to improve electronics assembly processes. The goal of this project is to visualize the behavior of an electronics assembly industry by simulating, visualizing the discrete events of the entire manufacturing processes and observing the flow of materials, size of buffers, and line balancing. The traditional scenario -- from the customer placing order for a product to delivery -- goes through various phases including manufacturing the product. Several major electronics manufacturing stages can be addressed: fabrication, assembly, testing, and packing. Each of these stages accounts for set up, process, failure, and wait time periods. A delay in one process will accumulate over to the future delays. To simulate the discrete events a general-purpose simulation system has been employed. For modeling and visualization CASUS (Computer Animation of Simulation Traces) system has been used developed by Fraunhofer Institute for Computer Graphics (Fraunhofer-IGD). This work focuses on the prototype interface between simulation trace file and CASUS animation scripts. The final system provides a 3-D visualization of electronics assembly processes based on event-oriented simulator data.