PCB Design for Advanced Semiconductor Package Technologies

The current market driver for semiconductor package technology is to provide more functionality and improve performance without increasing package size. Vertically configured 3D package technology addresses this issue for a broad number of enterprise products. Initially, the 3D package contained two or more semiconductor die elements mounted on top of one another most often interconnected using a common substrate interposer. Adapting through silicon via (TSV) technology for die-on-die interface on the other hand has the potential to further improve both package performance and package assembly efficiency. Progress in this area has accelerated through the cooperation and joint development programs between a number of government, industry and technical universities. An early high volume application for TSV was for the small CMOS image sensors used in wireless handsets to enable the vertical joining of the sensor and related logic element. Although the TSV process is touted as the 'next big thing' in semiconductor packaging, capabilities and methodologies for providing wafers and die elements for stacking currently vary a great deal between suppliers. Although TSV technology has the potential to revolutionize semiconductor packaging, it currently remains hostage to a very limited homogeneous family of products; MEMS, memory and image sensors. In addition, there are a number of processes and methodologies that are considered proprietary and may require licensing agreements and additional fees for their use. Industry roadmaps, however, continue to point toward the eventual use of TSV in developing new generations of high performance system-in-package products. What You Will Learn: This webinar will explore two basic approaches to TSV formation, via-first and via-last: Via-first integration forms very small via holes in the wafer during front-end processing. Via-last integration may occur before or after bonding wafers or joining individual die elements to one another (Die-on-Die). Due to the increased thickness of pre-joined die, the via-last process typically provides somewhat larger via holes than the via-first variation. Who Should View This Webinar: This Webinar has been developed specifically for product and circuit design professionals, systems engineers as well as assembly and test engineering specialists for OEM, ODM and EMS providers. About the presenter: Vern Solberg is a technical consultant for Invensas Corporation specializing in SMT and microelectronics design and manufacturing technology. Vern is a US delegate to the JISSO International Council (JIC) and is currently an active member of IEEE, SMTA, IMAPS and the IPC. He has served the industry for more than thirty years in areas related to both commercial and aerospace electronic products and is active as an author and educator. Solberg holds several patents for 3D semiconductor packaging innovations and is the author of Design Guidelines for Surface Mount and Fine-Pitch Technology and furnishes the 'Designers Notebook' column for SMT magazine. On Demand Webinar

Defect isolation and failure analysis is a key factor that drive development and manufacturing yield improvements in semiconductor packaging industry. From a manufacturing point of view, ensuring adequate package reliability is becoming more challenging due to increasing packaging complexity and a more pronounced impact from material physical property mismatch among packaging materials and components. The task of isolating defects and finding root cause is further complicated by ever shrinking feature sizes within the device and/or package, already approaching the nanometer range in contemporary semiconductor packages. Conventional failure analysis techniques such as physical cross sectioning or micro-cutting using focused ion beams(FIB) are sometimes no longer sufficient to find these defects. Both physical cross section and FIB are only capable of exposing the defect in two dimensions (x and y directions), which makes pinpointing the defect in depth, i.e., the z direction, extremely difficult when dealing defects with micron and submicron size. Additional complications are many times introduced during conventional sample preparation, which can introduce undesirable artifacts associated with the module and/or device depackaging. These artifacts may mask the true defects, or lead to misinterpretation of the true cause of failure. In this work, it has been determined that a three-dimensional failure analysis method is critical for finding some defects in silicon packages. For example, xenon difluoride (XeF2) has excellent selectivity to silicon and provides efficient material removal by chemical reaction, generating gaseous by-products that can be readily exhausted [1]. Furthermore, XeF2 has very little reaction with non-silicon materials, such as SiO2, and the metals and polymers commonly used in semiconductor devices and packages. This paper reports the application of XeF2 as an effective failure analysis technique to reveal defects in silicon packages. The mechanism of selective reaction between XeF2 and Si is discussed and key design features of the failure analysis tool are presented. The paper also highlights a few case studies which advantageously utilize XeF2 etching to expose defects. XeF2 was especially effective in detecting the source of electrical leakage in 3D packages having Through Silicon Via (TSV) structures. Due to its high etching selectivity to silicon, the leakage area in electrically failing samples was found to be due to damage of the TSV liner (passivation layer material) and further analysis reveals a three dimensional view of the TSV defect. With the addition of XeF2 etching, further characterization of defects by traditional methods such as FIB micro cutting also becomes more practical. The work suggests that a wider application of Si removal via XeF2 can be achieved by combining mechanical milling of bulk silicon followed by a final, low stress, silicon removal by XeF2 etching.

Volumetric nondestructive metrology for 3D semiconductor packaging: A review

While the semiconductor packages are evolving toward smaller package size and higher performance, the 3D IC or stacked-die packages are gaining popular. For these applications, IC wafers have to be ground to be relatively thin and the dies cut from these wafers have to possess sufficient strength against high stresses resulting from process handling, reliability testing, and operation. Hence, the strength of the dies, especially for the thin dies, has to be determined to ensure good reliability of the packages. Three-point bending test is widely used for measuring die strength; however the feasibility of the test is still questionable for determining strength of relatively thin dies. Meanwhile, the pin-on-elastic-foundation (PoEF) test [1] with special feature of bi-axial stress mode and elimination of the die edge effect has been proved more simple and reliable, but not for thin dies. In this study, the three-point bending test (under un-axial stress state) and the PoEF test (under bi-axial stress state) are evaluated for aiming at the thin-die strength determination which may features geometrical and contact nonlinearities. The feasibility of both test methods with their linear theories is evaluated by a nonlinear finite element method (NFEM) with taking into account geometrical and contact nonlinearities. The results show that these nonlinearities would cause an error of strength prediction by the linear beam theory for thin dies. For three-point bending test, the concept of moment equilibrium associated with the fitting equation for F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> extracted from the NFEM simulation is proposed and proved workable with good accuracy. The similar problem is faced in the PoEF test. The fitting equations based on the NFEM results are also proposed for calculating the strength of thin dies with better accuracy than theoretical formulation. Therefore, the nonlinearities has to be taken into account for both tests when the thin silicon dies are tested for strength.

The copper-based leadframe is practically proven effective in the thermal and reliability of a Quad Flat No Lead (QFN) three dimension (3D) stacked-die semiconductor package. Reducing the copper thickness is understood to present various thermal and reliability failure mode and mechanisms, such as die cracking and delamination. However, no in-depth study has been pursued in order to determine the capability of achieving the product requirements in terms of thermal and reliability in a 3D stacked-die package. The drive towards a Die-Free Package Cost (DFPC) reduction has led the authors to study the used of a thin leadframe in a QFN 3D stacked-die. Hence, the work presents basis for the qualification of a thin leadframe design and also to demonstrate the thermal and reliability performance. Finally, an extensive virtual thermal-mechanical prototyping has to be achieved in order to understand the physics of materials during the assembly and reliability testing of a 3D stacked-die package with a thin leadframe. This design rule was found to be developed in order to prevent a die crack occurrence between die and leadframe in the semiconductor package.

FlashSoldering is a new innovative, non-contact, localized reflow soldering process initially developed for terminating fine insulated copper magnet wires to electronic contacts without first removing the wire insulation. Subsequent research has extended FlashSoldering applications to joining fine magnet wires to high-speed data connectors, joining flexible ribbon cables to rigid printed circuit boards (PCB), and reflow soldering miniature surface mount (SMT) components and connectors to flexible or rigid PCB's. Four elements comprise the FlashSoldering System. The first element is the substrate, which can be a flexible or rigid PCB. The second element is the SMT component or connector with “gull wing” style leads or a flexible ribbon cable. The third element is a precise amount of solder. The solder is plated onto both the substrate or component leads or is mechanically attached to the component or connector leads in the form of a solder bearing “nugget” which may contain flux. Solder can also be applied in the form of a precise amount of dispensed solder paste. The fourth and final element is a diode laser heat source. Non-contact diode laser heat reflows the solder plating or solder bearing “nugget” on the SMT component to the substrate to complete the solder joint. Applications for FlashSoldering include: single and multiple toroidal transformer packaging; LAN filters; low power DC-DC converters; woven or braided high speed data cables; and miniature temperature sensitive SMT components, connectors, and flexible ribbon cable attachment to rigid or flexible PCB's.

Wafer level encapsulation is an important packaging process for several components in mobile and high-performance computing applications. In mobile applications, electronic components like application processors, radio-frequency System in Package (RF-SiP) and antenna modules are being manufactured using wafer level fan-out processes. In HPC, wafer level encapsulation is used for chip-on-wafer (CoW) processing and 2.5D / 3D packaging that enables wafer level packaging of processors and high band width memory devices. Although encapsulant materials are currently used in mass production, many pain points remain unresolved. These are predominantly related to lowering the wafer level warpage to enable better handling of wafers during processing, addressing the environmental and EU REACH regulatory compliance, providing better total cost of ownership to the end user by improving throughput and various other factors. In our development, we aim to address these pains and we will present our progress in this research paper. As the structural material in the package, molding compound can cause severe warpage issue during process, becoming the limiting factor to pursue thinner packaging design and causing serious wafer handling issues in the equipment during wafer processing. However, we considered a new material design route to develop ultra-low warpage LCM materials that can dramatically reduce the warpage thereby benefitting various WLP packaging design, such as Fan-in or Fan-out type. We have successfully demonstrated more than 70% improvement in warpage compared to traditional LCM compound. This new type of LCM material is REACH compliant and shows good warpage stability after high temperature annealing process. The polymer relaxation study shows the unique relaxation behavior leading to the warpage stability that is critical in many Fan-out processes. Dynamic Mechanical Analysis is the useful tool to study the relaxation behavior that can differentiate the impact of various chemistry on epoxy molding materials. Another key advantage of our LCM is the excellent gapfilling capability that can lead to the protection of high density structures in semiconductor packages with finer die-to-die or die-to-substrate spacing, meanwhile enabling low-warpage and simpler processing steps. Moreover, the new LCM design can help further shorten the molding time, allowing for increased throughput resulting in lower cost of ownership for the end users.

The goal of utilizing conductive inks to compliment traditional metallization approaches in semiconductor packaging applications is to enable ultimate design, functionality, and capital expenditures (CAPEX) flexibility through additive manufacturing without sacrificing performance or reliability. Traditional metallization processes include the sputtering method, a Physical Vapor Deposition (PVD) technique, and plating among others. PVD and electroless plating are currently the most used method to deposit a metal film in semiconductor packaging industry and it requires a complex, multi-step process. The metal films and patterns are required for electromagnetic interference (EMI) shielding and SAP among others. These processes have certain limitations related to technology factors including limits on panel area, uniform thickness on complex 3D shapes, temperature, patterning, health, and environmental factors as well as economic factors (throughput, CAPEX, footprint, maintenance, material waste and energy usage). Alternatively, technology is seeing a shift to jettable (aerosol jet and inkjet) or sprayable conductive inks for conformal shielding and additive, 3D metallization. This approach brings about substantial total cost of ownership and throughput advantages that will be reviewed in this paper as the ink-based processes (spray/jet) does not require vacuum and has relatively low process temperatures (at or below 180C in most cases). Metal complex conductive inks can be printed via various digital printing techniques such as aerosol jet printing, inkjet printing, and spray coating. The inks can be jetted or sprayed on various substrates e.g., 3D packages, wafers, chips, boards, and housings to provide a high-performance shielding layer that is reasonably priced and has outstanding reliability qualities for the semiconductor packaging industry. In this paper, we will review different printing techniques, and spray coating. We will review 5-sided metallization to provide shielding via spray coating, film performance parameters including coating thickness uniformity, EMI shielding effectiveness, adhesion to different substrates, and reliability. Another area of focus in this paper is using the silver metal complex inks in semi additive manufacturing as the silver MOD inks make an excellent seed layer for plating processes. We will discuss the spray coating process and performance of the silver film as the seed layer.

An electroless nickel (Ni)/electroless palladium (Pd)/immersion gold (Au) (ENEPIG) surface finish is widely applied to substrates used in various semiconductor packages. However, many issues have been arising in terms of solder joint reliability (SJR) during the assembly process. A number of factors can affect SJR such as thickness of each layer of ENEPIG, reflow profile, plating bath conditions, chemical composition of Pd and Ni layer, and chemical composition of solder balls. This paper focuses on investigating the influence of the factors on SJR and formation of intermetallic compounds (IMCs). The present study investigated the effect of the number of reflows (1, 3 and 5), Ni and Pd thickness of ENEPIG (Ni: 3, 6 and 9 µm, Pd: 0.02, 0.06 and 0.1 µm), chemical composition of Pd layer (pure Pd and Pd-phosphorus (P)) and chemical composition of solder balls (tin (Sn)0.7copper (Cu), SAC305 (Sn3.0 silver (Ag) 0.5Cu), SAC302 (Sn3.0Ag0.2Cu) and Sn3.5Ag). Special focus involved the combination of solder balls (SAC305 and Sn3.5 Ag) and chemical composition of the Pd layer (pure Pd and Pd-P). SJR that were evaluated through pull test and shear test, and then IMCs were observed through scanning electron microscope (SEM) analysis. The effect of Pd and Ni thickness with Pd-P and pure Pd was confirmed. Compared to Pd-P ENEPIG, a relatively high risk of SJR was found when using solder ball with no or low Cu content (e.g., SAC302 and Sn3.5Ag) and pure Pd ENEPIG. As a result of SEM analysis, Kirkendall voids were observed in the Ni <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> SnP IMC layer only on pure Pd ENEPIG with Sn3.5Ag solder balls and the fracture occurred along the void line. For Sn3.5Ag, a thicker P-rich layer (around 700 µm) was formed compared to SAC305 (300µm).

Current technology trend demands not only for high efficiency but also for portable devices, devices which can be carried and access anywhere and everywhere. This continues drives semiconductor's package towards miniaturization. One way is by placing active circuitry underneath the bond pads, this will reduce the die size, hence achieve lower cost per chip. This technology has led to the development of a more robust top metal that can withstand the high ultrasonic energy being applied in the bond pad. The use of thick copper power metallization in package design had shown significant benefits over the conventional aluminum top metal. Copper power metallization is a stack layer of thick copper (10um), nickel (2.0um) and gold (0.5um) plated over the top passivation layer. These prominently improve the overall device electrical performance with higher efficiency and lower Rds(on) by offering metallization with lower resistance and enables die size reduction of 10∼25% and provides flexibility which allows assembly of thicker bonding wires for high power applications. In copper power metallization, it helps in bondability and improves structural robustness especially with copper wire for underlying circuitry during the process. This paper presents the unique structure of this pad metallization, the challenges from die design phase and also looked at potential issues concerning passivation cracks and pad corrosions. This paper will also tackle how a stack layer of CuNiAu mitigates issues which are commonly encountered with Cu-Al bonding system (aluminum splash out issue, pad cratering and galvanic corrosion). The overall component interface integrity for this new metallization is unknown to us. Detail simulations were carried out to understand the system stress generated between the copper power pad and silicon (Si) die which affect the passivation integrity as well. Detail characterizations will be discussed to understand the ratcheting mechanism and its resolution. Assessment on package integrity with Moisture Level Sensitive (MSL1) condition was done to ensure it is well integrated with currently assembly process and material used with no delamination found.

The challenges for the companies involved in conception, development and/or manufacturing of electronic products are the lead-free technology with its increased melting temperature of the solder alloy and trend to reduce the solder materials cost by usage of lead-free solder pastes with low silver content. Defining the elements Pad-Paste-Pin-Process as Key Process Input Variables (KPIV) in terms of 4P Soldering Model concept [1, 3], the solder joints are result of KPIV synergistically interactions and correlations, with consequences over their microstructure. In the paper, taking into consideration the cooling rate influence over intermetallic compounds formation and microstructure, are presented the investigations over electrical, and mechanical properties of solder joints resulted from Vapour Phase Soldering (VPS) process in terms of 4P Soldering Model. Maintaining PAD and PIN of KPIV as references were study the solder joints properties determined by PASTEs as function of cooling rate parameters of VPS PROCESS. The results of the studies performed and presented in the paper will be used for improving process control in order to minimize losses on VPS lines, to reduce defects numbers and rework time in order to achieve "zero defects production".

With the rapid development of IC technologies, topics of 3D stacked IC packages are now being studied vastly around the world. In 3D stacked IC technologies, many electrical characteristics have been proved to have great improvements, but their corresponding thermo-mechanical problems are raising as well. Due to the reason of ICs stacking, thermo-mechanical problems are becoming more serious than those in traditional single IC package. These problems include the heat dissipation, die breaking, interfacial delamination, via cracking and so on. These corresponding problems not only cause failures in 3D stacked IC packages but also have significant influences on reliability. For the sake of realizing critical stress distributions in 3D stacked IC packages, the three dimensional finite element analysis (FEA) modeling has been employed in this paper. The 3D-WLP (wafer-level-package) with ten layer chips stacking is selected as our test vehicle. By using three dimensional FEA modeling, thermal induced stress distributions in 3D-WLP when subjected to a uniform temperature change can be illustrated. Further, the design of experiments (DOE) analysis for design optimization has also been used to obtain the sensitivities of geometry and material properties of 3D-WLP. Several geometric dimensions and material properties are selected as main design factors and the average value of maximum von Mises stress in copper vias and chips is chosen as the response to be optimized. Through the DOE analysis, the optimum geometry and material properties of 3D-WLP and this result in smaller von Mises stresses in copper via and chip configurations can be obtained. These results can be most effectively used as design guidelines to engineers when optimum stress solutions in 3D-WLP are required.

With the rapid development of electronic and electrical products, the working frequency of ite products is higher and higher, the influence frequency range of interference between electronic products is also expanding, the test frequency range of radiation anti-interference is improving, at the same time, more and more attention is paid to the requirements of radiation anti-interference test site. At present, the uniformity of radiation field is mainly realized by single point multiple test, which will inevitably lead to the measurement error due to the time-varying characteristics of the radiation signal itself; In addition, the test time is greatly increased and the test efficiency is low. In order to solve these problems, this paper designs a device which can realize multi-point test at one time and can automatically adjust the test area. The simulation shows that the device can meet the requirement of 9point uniformity test of radiation field in 500mm × 500mm ~ 1500mm × 1500mm area. On this basis, experiments are carried out in 1000mm × 1000mm test area for 1.35GHz and 2.88GHz. The experiments show that the test device can meet the requirement of 9point uniformity test and greatly improve the test efficiency and automation.

Reliability challenges in 3D IC packaging technology

Universal Instruments Corp's Advanced Process Laboratory has observed countless failures in electronics manufacturing. From fine pitch printing, to PoP, 01005 defects, and high Tg laminate failures. These failures combined with internal research have provided a unique perspective for design for manufacturability and reliability. These lessons will be presented to the class when we discuss material selection, current electronics research, and failure analysis case studies. We will touch on design considerations for many advanced assembly processes as well as discussing types of analytical techniques that can be used for materials characterization. Topics Covered: What are the major difficulties in lead-free reliability testing Mixed alloy assembly best practices PCB plating considerations Analytical testing techniques and what they can identify root causes for production failures. Lead-free laminate selection and testing procedures: Can your board withstand 9x reflow? Learned lessons from actual failure analysis case studies Suggestion: Please bring specific questions or examples of surface mount process difficulties you are willing to share for an open discussion at the end of class. In my experience many problems can be solved with a brief discussion of the issues. Instructor Bio: Since 2002 Martin has been working in electronics Failure Analysis and currently oversees all the failure analysis projects for the Universal Instruments Corporation's Advanced Process Lab (APL). Martin's surface mount assembly process knowledge and formal education in Mechanical Engineering, Materials Science, and Physics has given him a unique background for the determination of root cause in electronics. Martin has worked with some of the world's largest electronics manufacturers not only determining root cause, but to also implementing process, design, parts, and materials changes in order to improve end product quality, reliability, and manufacturability. On Demand Webinar