Algorithm-architecture co-design by example: a coprocessor for on-line arithmetic

Software defined radio (SDR) is characterized by its flexibility and convenience of modification, because significant amounts of signal processing are handed over to the general-purpose processor (GPP), rather than being done in special-purpose hardware. In the long term, software-defined radios work well in low data transmission rate systems such as 2G/3G cellular systems and other wireless radio systems. With rapid development of GPP power, more complex algorithms and higher data rate wireless communication systems can be implemented with GPP processor and general purpose RF front end. In this paper we propose a LTE physical layer parallel system architecture based on multicore GPP to match up the high capacity requests of LTE air interface. Firstly, we analyzed the complexity of each LTE physical layer module and made a statistics of their processing time. And then we used Linux CPU affinity to allocate each LTE module to particular CPU core carefully based on the statistics. CPU utilization rate shows that using multi-core makes the system to have enough capacity. Our system can only match up 2M bandwidth when the LTE physical layer procedures are running on single CPU core, while it can match up 5M bandwidth when it's running on multi-core.

The dissertation presents a new parallel programming paradigm for developing high performance (HPC) applications on the Grid. We address the question How to tailor HPC applications to the Grid? where the heterogeneity and the large scale of resources are the two main issues. We respond to the question at two different levels: the programming tool level and the parallelization concept level. At the programming tool level, the adaptation of applications to the Grid environment consists of two forms: either the application components should somehow decompose dynamically based on the available resources; or the components should be able to ask the infrastructure to select automatically the suitable resources by providing descriptive information about the resource requirements. These two forms of adaptation lead to the parallel object model on which resource requirements are integrated into shareable distributed objects under the form of object descriptions. We develop a tool called ParoC++ that implements the parallel object model. ParoC++ provides a comprehensive object-oriented infrastructure for developing and integrating HPC applications, for managing the Grid environment and for executing applications on the Grid. At the parallelization concept level, we investigate the parallelization scheme which provides the user a method to express the parallelism to satisfy the user specified time constraints for a class of problems with known (or well-estimated) complexities on the Grid. The parallelization scheme is constructed on the following two principal elements: the decomposition tree which represents the multi-level decomposition and the decomposition dependency graph which defines the partial order of execution within each decomposition. Through the scheme, the parallelism grain will be automatically chosen based on the available resources at run-time. The parallelization scheme framework has been implemented using the ParoC++. This framework provides a high level abstraction which hides all of the complexities of the Grid environment so that users can focus on the logic of their problems. The dissertation has been accompanied with a series of benchmarks and two real life applications from image analysis for real-time textile manufacturing and from snow simulation and avalanche warning. The results show the effectiveness of ParoC++ on developing high performance computing applications and in particular for solving the time constraint problems on the Grid.

Development of dimethylsiloxane based tetraglycidyl epoxy nanocomposites for high performance, aerospace and advanced engineering applications

Switched reluctance machines (SRMs) have been extensively researched for high performance aerospace applications because of their inherent fault tolerance. Recent work by the authors suggests that with careful design a similar degree of fault tolerance may be achieved with a permanent magnet machine (PM) at a significantly higher torque density than its SRM counterpart. This latter suggestion is of crucial importance in high performance applications, such as aerospace, where a low mass is essential. This paper is concerned with reporting measured results from a fault tolerant PM machine, and using these results to examine the relative merits of SR and PM technology for this application.

This paper discusses the performance analysis of Gate Electrode Workfunction Engineered (GEWE) Silicon Nanowire (SiNW) MOSFET using device simulation software: ATLAS-3D in terms of static performance. The following performance metrics are studied: transconductance, conduction current density, potential, electron temperature and electric field. The effectiveness of GEWE-SiNW design was scrutinized by comparing it with conventional SiNW MOSFET. It is found that with the incorporation of GEWE scheme onto SiNW, it improves the conduction current density thus enhances the device current capability. In addition, device CV behaviour is also analyzed as a function of gate and drain bias voltage. This analysis is studied with an aim to optimize the gate length and oxide thickness for improved high-performance applications. It is perceived from the results that as gate length scales down to 10 nm and oxide thickness at 1.5 nm, both Cgs and Cgd reduce appreciably owing to low off current and high on current. Thus, GEWE-SiNW device paves the way for high switching performance applications.

We have proposed and evaluated a scalable architecture for implementing multi-gigabit protocol engines. The architecture utilizes a combination of custom-made VLSI circuitry and a general-purpose processor, such as the Intel 960 or the IBM PowerPC 403. Time critical operations such as line coding/decoding, CRC generation/checking, context-independent header processing, and buffer management are implemented in the customized VLSI part. These designs are never-the-less scalable and can be cascaded to further increase throughput. Some of the packet level processing, such as context-dependent header processing, are performed by the general-purpose processor. As processing power increases, more and more functions can be included in the general purpose processor. The throughput of this architecture is shown to be adequate for the operations and bit rates currently specified by Fibre Channel. Future CMOS technology advances will have the potential to further improve the raw throughput.

New media and signal processing applications demand ever higher performance while operating within the tight power constraints of mobile devices. A range of hardware implementations is available to deliver computation with varying degrees of area and power efficiency, from general-purpose processors to application-specific integrated circuits (ASICs). The tradeoff of moving towards more efficient customized solutions such as ASICs is the lack of flexibility in terms of hardware reusability and programmability. In this paper, we propose a customized semi-programmable loop accelerator architecture that exploits the efficiency gains available through high levels of customization, while maintaining sufficient flexibility to execute multiple similar loops. A customized instance of the loop accelerator architecture is generated for a particular loop and then the data and control paths are proactively generalized in an efficient manner to increase flexibility. A compiler mapping phase is then able to map other loops onto the same hardware. The efficiency of the programmable accelerator is compared with non-programmable accelerators and with the OpenRISC 1200 general purpose processor. The programmable accelerator is able to achieve up to 34x better power efficiency and 30x better area efficiency than a simple general purpose processor, while trading off as little as 2x power and area efficiency to the non-programmable accelerator.

We have implemented a high performance Prolog engine by directly executing in microcode the constructs of Warren's Abstract Machine. The implementation vehicle is the VAX 8600 computer. The VAX 8600 is a general purpose processor containing 8K words of writable control store. In our system, each of the Warren Abstract Machine instructions is implemented as a VAX 8600 machine level instruction. Other Prolog built-ins are either implemented directly in microcode or executed by the general VAX instruction set. Initial results indicate that our system is the fastest implementation of Prolog on a commercially available general purpose processor.

In this paper, we present a quantitative study that investigates implementation of a layer-2 switching application on a general purpose processor (GPP). The objective is to better understand the main challenges and tradeoffs in using such processors for packet processing applications. The goal of this study is to identify the architectural guidelines for successful development of an application specific instruction processor (ASIP) for such applications. To asses the performance of switching of packets with various lengths, a LEON2 RISC processor has been chosen as a GPP. The obtained results are compared together based on detailed instruction level profiling of the mentioned application.

We present experimental results on FPGA use in special and general purpose processors, using as case studies a computational accelerator for gene sequence analysis, an integer implementation of the DLX microprocessor and a real-time signal processor for rocket telemetry. All these devices have been successfully prototyped, and are now completely functional. We present detailed analysis of our experience with FPGAs in these machines, describing savings in chip count, power consumption, area, and cost. For all quantitites except cost, measured savings were typically an order of magnitude improvement over discrete IC implementations. References

Parallel implementations of Brunotte’s algorithm

Improving performance of codes with large/irregular stride memory access patterns via high performance reconfigurable computers

HiPeC — High Performance Cryptographic Service for Heterogeneous Network-on-Chip Systems

Many problems involving network design can be found in the real world, such as electric power circuit planning, telecommunications and phylogenetic trees. In general, solutions for these problems are modeled as forests represented by a graph manipulating thousands or millions of input variables, making it hard to obtain the solutions in a reasonable time. To overcome this restriction, Evolutionary Algorithms (EAs) with dynamic data structures (encodings) have been widely investigated to increase the performance of EAs for Network Design Problems (NDPs). In this context, this paper proposes a parallelization of the node-depth encoding (NDE), a data structure especially designed for NDPs. Based on the NDE the authors have developed a parallel algorithm and a hardware architecture implemented on FPGA (Field-Programmable Gate Array), denominated Hardware Parallelized NDE (HP-NDE). The running times obtained in a general purpose processor (GPP) and the HP-NDE are compared. The results show a significant speedup in relation to the GPP solution, solving NDP in a time limited by a constant. Such time upper bound can be satisfied for any size of network until the hardware resources available on the FPGA are depleted. The authors evaluated the HP-NDE on a Stratix IV FPGA with networks containing up to 2048 nodes.

Collaboration of reconfigurable processors in grid computing: Theory and application