An Accurate Digital Predistortion for Wideband Power Amplifiers Based on Directly Solving the Inverse Model Function

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

The application of digital predistortion in base band signal is an extended method of amplifier linearization to reduce the adjacent channel interference (ACI) in those systems in which a varying envelope modulation scheme like OFDM and MQAM is used. Digital baseband predistortion is a highly cost-effective way to linearize power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored. In this paper we proposed a new technique for adaptation of digital predistorter that considers memory effects in power amplifiers. This method is a combination of two techniques, memory polynomial predistortion and slope-dependent method. This new technique is validated by using a 1.9 GHz 60W LDMOS power amplifier and various signals such as 2-carrier and 3-carrier CDMA.

Power amplifiers (PAs) are inherently nonlinear devices and are used in all transmitters of a communications equipment. To improve the performance of telecommunication channels, digital baseband predistortion is employed to compensate for PA nonlinearities. But most existing architectures base on the memoryless PA model. For wideband signal transmission, PA memory effects can no longer be ignored and memoryless predistortion has poor performance. In this paper, a predistortion scheme based on the indirect learning architecture is proposed and analyzed with application to the wideband wireless transmitter. Then the performance of overall transmitter system is verified by simulation results. The measurement shows that, when inputting a single carrier WCDMA signal with 5 MHz bandwidth, good AM-AM and AM-PM performance and roughly 20 dB improvement of out-of-distortion at an offset frequency of 5 MHz were achieved, after adding the proposed predistortion method.

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents a quantitative metric for memory effects in power amplifiers (PAs) and applies it to various active device technologies and wireless system contexts. The proposed metric is mathematically founded in the dynamic two-tone distortion response, has a clear physical meaning in the important field of PA linearization and can be easily evaluated from either harmonic balance simulations or measurement data gathered in a microwave laboratory. In addition, a memoryless PA linearizer, optimum for reducing the integrated intermodulation distortion (IMD) power in the operation bandwidth for a two-tone excitation, is derived, providing a rigorous figure-of-merit of PA linearizability under static IMD compensation. The application of this figure-of-merit is then illustrated for three different PA prototypes based on Si LDMOS, InGaP/GaAs heterojunction bipolar transistors, and GaN high electron-mobility transistors, designed for 900-MHz (global system for mobile communications), 2.1-GHz (wideband code division multiple access), and 3.5-GHz (WiMax) wireless systems, respectively. </para>

The decomposed vector rotation (DVR) model is proposed for digital predistortion (DPD) to compensate for the nonlinearities and memory effects of Power Amplifiers (PA). In this paper, we propose a new neighborhood definition for the DVR model that allows to extend the hill climbing (HC) algorithm to find the optimal structure of DVR model which provides the best compromise between modeling accuracy and complexity. The convergence of the algorithm has been verified and validated using real measurements from Class-AB PA.

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

We consider digital predistortion (DPD) for linearizing power amplifiers (PAs) of hybrid MIMO systems with subarrays. Designing such a DPD scheme is difficult because one DPD should linearize all PAs of a subarray whose beamforming coefficients are time-varying. We develop an adaptive DPD technique for each subarray based on direct learning method minimizing the sum of squared errors between the input and output signals of PAs. Use of the least mean square (LMS) Newton algorithm is proposed to adaptively control the DPD parameters. It is shown that the proposed DPD can simultaneously linearize multiple PAs in a subarray irrespective of its beamforming coefficients. Computer simulation results demonstrate that the proposed scheme can perform better than an alternative scheme that designs the DPD based on one of the PA outputs and uses the resulting DPD for all PAs of the subarray.

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Radio frequency power amplifier (PA) is an important part of the transmitter system, which can drive numerous output devices. However, the nonlinear characteristics of PA will cause serious harmonic interference, which leads to electromagnetic interference (EMI) problems. In this article, the nonlinear characteristics and the memory effect of PA are analyzed. The strong nonlinearity region and the weak nonlinearity region are divided according to the strength of the nonlinearity. For the strong nonlinearity, an encoder–decoder-based (E-D-based) artificial neural network model is proposed to predict the harmonic interference of PA. To promote the prediction of high-order harmonics when the input signal is small, a multilayer perceptron model is used for the weak nonlinearity region. The models can effectively predict the first five harmonics of PA, in which the mean absolute error of the fundamental wave is about 0.1 dB, the one of the second-order and the third-order harmonics is about 0.5 dB. Since transfer learning (TL) can simplify the training of the model based on the similarity of different tasks, TL based on model transfer is used to predict the harmonic interference of other PAs according to the existing models. The amount of data required for the modeling of PA can be greatly reduced and the accuracy of prediction can be guaranteed by applying TL. Ultimately, the proposed method can predict the harmonic interference rapidly and accurately according to the known excitation signal so that corresponding measures can be taken to avoid the influence of radiated spurious emission on the use of the sensitive receiving devices in the same electromagnetic environment.

This paper investigates the trade-off between power amplifier (PA) nonlinearity, output power backoff (OBO), digital predistortion (DPD), and clipping and filtering (CF) in terms of energy consumption. The energy efficiency of a PA depends on the OBO of the signal and usually increases as the OBO decreases. Peak to average power ratio (PAPR) reduction methods like CF and PA linearization algorithms like DPD methods allow the use of a smaller OBO. Those algorithms show best results when used together. By studying the trade-off between the power consumed in the CF and DPD circuits versus having a larger OBO for a target bit-error rate (BER), we show that below a certain PA output power the power consumption is not reduced by decreasing the OBO. We also show that the increase in distortion noise when using DPD and CF might defeat the purpose of their use in terms of power consumption. Given the trend toward smaller cells like femtocells, requiring less output power, CF and DPD may not be required at all, leading to a simpler and power saving transmitter design.

In this paper, an efficient method to characterize electrical memory effects arising from the interaction between the static nonlinearity and the frequency response is proposed using a multi-tone measurement. A transmitter system with nonlinear power amplifier (PA) is modeled with two box Wiener structure that consists of a static Saleh model and a linear filter. A nonlinear least square method with a multi-tone measurement is used to extract frequency response and nonlinear characteristics. The proposed method is verified with a simulation and experiment with a 10W class AB gallium-nitride (GaN) HEMT PA.

Design of high-efficiency power amplifier (PA) is one of the key challenges to realize green radios, wherein digital predistortion (DPD) is deployed to reduce the PA’s power back-off and thus increase its power efficiency. As the bandwidth of the transmit signal increases, stringent requirements are posed on the DPD linearization performance with limited sampling rate and dynamic range for the analog-to-digital converter (ADC) in the DPD feedback channel. In this paper, under a fixed ADC sampling rate, novel DPD architecture is proposed to compensate for the PA nonlinearity with limited ADC dynamic range. In the feedback channel of the proposed architecture, an extra radio frequency (RF) cancellation chain is introduced to eliminate the linear component of the PA amplified signal, and thus the requirement on the ADC dynamic range can be significantly reduced. Subsequently, by accurately estimating the loop delay and attenuation of the cancellation chain, the baseband replica of the RF cancelling signal is recovered, and the original PA output signal is rebuilt to estimate the DPD coefficients. Finally, experiments show that for the long term evolution (LTE)-advanced signals, the proposed architecture can achieve an adjacent channel leakage ratio lower than −47.6 dBc, which outperforms the conventional DPD by about 3.4 dB, with the effective bits of the ADC being reduced by 4.4 and a power added efficiency of 43.8% with 7.3 dB power back-off being observed for a fabricated Doherty PA with 50-dBm saturation power.

The inherent nonlinear behavior exhibited by power amplifiers (PAs) in saturation mode is a major impediment in wireless systems to achieve higher power efficiency, and higher spectral efficiency. Although PA behavioral modeling and digital predistortion (DPD) techniques are widely utilized at transmitter to characterize and linearize such distorted nonlinear output of PAs, the nonlinear distortions with memory effects have become more severe due to simultaneous strong crosstalk between multiple PA branches in multiple-input multiple-output (MIMO) arrays. Furthermore, current multi-input behavioral models suffer from a sharp increase in number of coefficients as the number of transmitter path increases in MIMO. In overcoming these challenges, we propose a decomposed cross-correlation based single-input-single-output (CC-SISO) behavioral modeling architecture. The proposed solution utilizes a low-cost, novel cross-correlation based method to estimate and cancel the simultaneous nonlinear and reverse crosstalk from multiple PA branches. Once the crosstalk is mitigated, the MIMO DPD can be implemented with single-input DPD blocks which significantly reduces the complexity. Furthermore, CC-SISO DPD eliminates the requirement for signal feedback paths before and after the PA, and thus reduces overall hardware implementation complexity. Through simulations, we demonstrate that the proposed CC-SISO architecture can reduce the overall complexity of state-of-art multi-input DPD models for MIMO systems.

Digital predistortion (DPD) exploiting the Volterra series can effectively compensate the strong nonlinearities (with memory effects) of power amplifiers. Diverse pruning schemes have been proposed to reduce the computational complexity with comparative performances. Regrettably, the mechanism of basis construction in different DPDs that is related to the complexity-efficiency tradeoff has not been well-studied. In order to compare methodically the Volterra-series based DPDs, the key parameters of the basis are studied here. Especially for the cross terms that describe the interaction between nonlinearities and memory effect, the complexity-efficiency tradeoff cannot be addressed directly. Thus, the basis construction of DPDs is firstly mapped to the general Volterra-series to observe the pruning property of each DPD. The diagonal dispersal property on basis construction is concluded as the most efficient and reliable way for pruning DPD techniques. The running complexity-accuracy tradeoff is quantitatively analyzed via the number of floating point operations. With the best performance settings found by the Qhull algorithm, the experimental results show that (1) the nonlinear order of the cross terms is more significant than the related memory depth, and (2) basis construction with diagonal dispersal properties effectively shows the complexity-efficiency tradeoff of different DPDs. These results offer new angles to assess the feasibility of DPDs and their involved complexity.

In this letter, a novel model is proposed for modeling the nonlinearity and memory effects of power amplifiers. The classical Volterra model is modified through a function of the sum of nonlinearity order with sum of memory length. The parameters of this model can be extracted in digital domain since the model is analyzed based on the envelope signals. The model we proposed enables a substantial reduction in the number of coefficients involved, and with excellent accuracy.