A New Block-Oriented Model for Reduced Complexity Digital Predistortion in Wideband Applications

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

The application of digital predistortion in base band signal is an extended method of amplifier linearization to reduce the adjacent channel interference (ACI) in those systems in which a varying envelope modulation scheme like OFDM and MQAM is used. Digital baseband predistortion is a highly cost-effective way to linearize power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored. In this paper we proposed a new technique for adaptation of digital predistorter that considers memory effects in power amplifiers. This method is a combination of two techniques, memory polynomial predistortion and slope-dependent method. This new technique is validated by using a 1.9 GHz 60W LDMOS power amplifier and various signals such as 2-carrier and 3-carrier CDMA.

New mobile applications require the use of Radio Frequency Power Amplifiers (RF PA) in a context of reconfigurability and adaptability. In this paper, we propose a modeling study of RF PA in this context. The proposed approach is a combination of a Feedback-Wiener (FW) structure with a Memory Polynomial (MP) model, which gives a pruned Volterra series. A FIR filter is used in the FW model as a feedback path to reproduce the PA memory effects. Also, a recursive identification algorithm based on the key-term separation principle is proposed and used for an experimental characterization of an LDMOS PA (50W–500MHz to 2.5GHz), with different carrier frequencies, bandwidths and output powers. The comparison with a conventional Generalized Memory Polynomial model (GMP) shows that the proposed model presents the same performances in term of behavioral modeling, with the advantage of a reduced number of parameters.

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.

<span lang="EN-US">In this paper, a low-complexity model is proposed for linearizing power amplifiers with memory effects using the digital predistortion (DPD) technique. In the proposed model, the linear, low-order nonlinear and high-order nonlinear memory effects are computed separately to provide flexibility in controlling the model parameters so that both high performance and low model complexity can be achieved. The performance of the proposed model is assessed based on experimental measurements of a commercial class AB power amplifier by applying a single-carrier wideband code division multiple access (WCDMA) signal. The linearity performance and the model complexity of the proposed model are compared with the memory polynomial (MP) model and the DPD with single-feedback model. The experimental results show that the proposed model outperforms the latter model by 5 dB in terms of adjacent channel leakage power ratio (ACLR) with comparable complexity. Compared to MP model, the proposed model shows improved ACLR performance by 10.8 dB with a reduction in the complexity by 17% in terms of number of floating-point operations (FLOPs) and 18% in terms of number of model coefficients.</span>

This article investigates the issue of low-cost digital predistortion (DPD) implementation in fixed-point field programmable gate array (FPGA) by considering the bit-resolution along with lower number of coefficients. The impact of principle component analysis (PCA) on bit-resolution of DPD solution is proposed within the context of established DPD models. Unlike previously proposed PCA based solutions, it is established by simulation and measurement that the numerical stability problem associated with popular models such as memory polynomial (MP) can be alleviated when PCA is applied to the observation data matrix. It is reported with measurement results that PCA based model provides better linearization performance with the least memory size requirement and number of LUTs in 16-bit fixed-point FPGA operation than MP, orthogonal memory polynomial (OMP), and generalized memory polynomial (GMP) models. The performance of the proposed model, is evaluated in terms of normalized mean square error, adjacent channel error power ratio, matrix condition number, and dispersion coefficient for continuous Class-AB and ZX60-V63+ power amplifiers using wide code-division multiple access signal (WCDMA) and long term evolution (LTE) signal with peak-to-average-power ratio (PAPR) around 9.895 and 11.92 dB, respectively.

Power amplifier (PA) nonlinearities and the digital predistortion (DPD) required for linearization are modeled at baseband using the memoryless polynomial, memory polynomial, and pruned Volterra series. The sampling requirements for the nonlinear basis waveforms created from a band-limited signal are determined as a function of the polynomial order. A Gaussian approximation of the channel filtering is used to make the mathematical analysis tractable. For the memory polynomial and pruned Volterra series cases, the spacing between memory taps, referred to as the delay offset, is selected to trade off model accuracy and the condition number of the coefficient estimation. Examples are provided showing how to select the appropriate delay offset for a memory-based amplifier model and its effect on the DPD performance. A pruned Volterra series is proposed, which demonstrates improved DPD performance compared with the memory polynomial.

The paper presents the results of laboratory studies on influence of DC transistor operating conditions both on power amplifier (PA) linearity and effectiveness of digital predistortion procedure. The impact of DC operating conditions of 10 W GaN HEMT power amplifier on nonlinearity factors without and with digital predistortion (DPD) were investigated. The obtained results show that there is an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor. However, some noticeable improvement of ACLR with significant increase in PA power added efficiency (PAE) is obtained for PA with digital predistortion.

This paper expounds a complexity-reduced generalized memory polynomial (CR-GMP) model for multi-band power amplifier (PA) digital predistortion (DPD). First, PA block diagrams characterizing the behavior of PAs under multi-band stimulus are proposed. Second, CR-GMP forward models are derived from the feedback block diagrams of the PA, driven with both dual- and tri-band signals, leading to a general formulation for PAs driven with multi-band signals. The resulting models are used to linearize two PAs driven with dual- and tri-band signals. The proposed CR-GMP models are compared to a dual-input digital predistortion (2D-DPD) model and a triple-input digital predistortion (3D-DPD) model and show similar linearization performance while requiring fewer coefficients. Due to the presence of cross terms in the dual-band CR-GMP formulation, the proposed model is robust against time-delay misalignment between dual-band signals, whereas the 2D-DPD is not. With a reduced number of coefficients and the presence of cross terms, the proposed CR-GMP models represent excellent candidates for the linearization of highly nonlinear PAs driven with multi-band signals.

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

This paper presents a compact transformer-based linear and efficient power amplifier (PA) in 0.13-μm SiGe:C BiCMOS for 5G applications. To reduce the form factor, an ultra-compact neutralized cascode PA core is proposed, which achieves a state-of-the-art power density. To obtain a gain flatness at 5G NR band n257 (26.50-29.50GHz), transformer-based input and output matching networks are designed. The PA demonstrates a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$S_{21}$</tex> 3-dB bandwidth <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(BW_{-3\text{dB}})$</tex> of 10.5GHz from 23.5 to 34GHz. At 28GHz/29GHz, the saturated output power ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\text{sat}}$</tex> ) are 22.7/22.4dBm with power-added efficiency (PAE) of 38.1/39.8%. The PA also supports 64- and 256-QAM modulated signal tests without digital pre-distortion (DPD). Over 26-30GHz, for 4.8Gb/s 64-QAM signals with peak-to-average power ratio (PAPR) 8.3dB at −25dB EVM, this PA continuously achieves >16dBm average power ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{\text{avg}}$</tex> ) with >11% PAE.

Digital predistortion (DPD) technique is an effective means to alleviate the nonlinearity of power amplifiers (PAs) and improve transmitter efficiency. However, for orthogonal frequency division multiplexing (OFDM) systems with a high peak-to-average power ratio (PAPR), the PAPR reduction needs to be deployed in combination with DPD, to maximize transmitter efficiency. The extra complexity caused by the introduction of PAPR reduction on the main road has become a non-negligible defect. To address this issue, this letter proposes a joint PAPR reduction and DPD model based on the generalized memory polynomial (GMP). To train the joint GMP model, this letter improves the ping-pong joint optimization (P2JO) approach under the offline case, to obtain accurate training data. The comparative experimental results based on 100-MHz Doherty PA show that the proposed joint model significantly reduces the model complexity on the main road, while ensuring adjacent channel power ratio (ACPR) and bit error rate (BER).

Cascaded digital predistortion can reduce the pre-distorter model complexity while keeping the linearization performance. This paper evaluates the performance of cascaded DPD with a high nonlinear power amplifier (PA). A 2-stage memory polynomial (MP) model DPD structure is analyzed and compared with a single stage MP and generalized memory polynomial (GMP) model DPD. The linearization performances of the identified DPDs are evaluated in terms of improvement on adjacent channel power ratio (ACPR) and error vector magnitude (EVM). Tests are done on a Doherty power amplifier with a Long Term Evolution-Advanced (LTE). The computational complexity and the convergence speed of the DPD identification are discussed.

The crosstalk and transceiver noise is an intrinsic part of the multiple-input and multiple-output (MIMO) System, becoming more prominent in low-cost systems. Moreover, the power amplifiers (PAs) cause nonlinearity, propagating to the complete chain. The conventional techniques do not provide the joint method for crosstalk, transceiver noise, and PA nonlinearity. This results in the performance limitation of the digital predistortion (DPD). Hence we propose a wavelet multiscale principal component analysis (PCA) based technique to deal with such problems (crosstalk, transceiver noise, and system nonlinearities). It is reported using measurement and simulation that numerical stability issue is no longer an issue when wavelet multiscale PCA-based DPD is applied. The effect of wavelet multiscale PCA on bit-resolution of DPD is shown to be better than established DPD Models. On a field-programmable gate array and direct conversion transceiver-based platform, the performance of the proposed model is analyzed using PA. Parameters like normalized mean square error have shown an improvement of around 23 dB and adjacent channel error power ratio has shown an improvement of around 22 dBc for a ZX60-V63+ power amplifier using LTE-OFDM signals.

Theoretically, memoryless nonlinear effect is the main concern for RF power amplifier (PA) modelling and analysis. However, the latest generation wireless communication systems, such as Wi-Fi, WiMAX and LTE, using wider bandwidth, add new problems for the analysis of RF PAs, which is the memory effect associated with the bandwidth. The memory effect causes additional distortion to the PA and affects the performance of digital predistortion (DPD) design. Previously, we predicted the memoryless spectrum regrowth of a PA related to its intercept points up to arbitrary high order for a few of wireless communication signals, such as TDMA, CMDA and OFDM. In this letter, we propose a simplified Hammerstein structure-based method to consider the memory effect as well in order to analyse the nonlinear characteristic of PAs more precisely and completely. The simplification greatly reduced the complexity of classic Hammerstein system identification for PAs. The result will be useful in the analysis of RF PAs with memory effect and the proposed PA model is intended to be used in predistorter design for modern wideband wireless communication systems.