Sampling requirements for nonlinear basis waveforms used in digital predistortion and amplifier modeling

International audience

Digital predistortion (DPD), based on complex-valued memory polynomials (MP), is established as an efficient method for power amplifier (PA) linearization. The DPD facilitates compliance of the telecommunication infrastructure to strict standard specifications (transmit spectrum mask (TSM), error vector magnitude (EVM), bit error rate (BER), [Formula: see text]) by making PA more linear, while at the same time reduces the running cost of the wireless infrastructure (at both Base Transceiver Station (BTS) and User Equipment (UE) sides) by making PA more power efficient. Even when DPD is utilized, signals with high peak-to-average power ratio (PAPR) produce out-of-band PA spectrum emission due to intermodulation products affecting all above-mentioned critical standard specified parameters. The novelty proposed in this paper is as follows. PA is restricted to operate within “reasonably above” PA linear region using PAPR reduction technique. The residual nonlinearity is taken care of by DPD. The combination of DPD and PAPR PA linearization methods is implemented on software-defined radio board. The necessary steps for efficient PA linearization are presented, compensating both out-of-band and in-band signal distortions. We achieved EVM = 2.0%, ACPR [Formula: see text]50[Formula: see text]dBc, at 10[Formula: see text]W LTE modulated PA output, antenna point and PA output power of 39.5[Formula: see text]dBm.

Two novel models with lower complexity are proposed for linearization of 2×2 MIMO transmitters with nonlinear crosstalk. Crossover modified memory polynomial (COMMP) model is introduced as an extension of the 2-D modified memory polynomial (2-D MMP) model and COMMP-CPWL model is derived from the COMMP model but without high-order terms which are replaced by the canonical piecewise linear function. Genetic Algorithm (GA) is used to achieve optimal digital predistortion (DPD) performance and least-square (LS) algorithm is adopted to extract the models coefficients. Experimental results show that both models can achieve nearly the same DPD performance and model accuracy as the 2×2 Parallel Hammerstein (PH) model while requiring fewer model coefficients.

New mobile applications require the use of Radio Frequency Power Amplifiers (RF PA) in a context of reconfigurability and adaptability. In this paper, we propose a modeling study of RF PA in this context. The proposed approach is a combination of a Feedback-Wiener (FW) structure with a Memory Polynomial (MP) model, which gives a pruned Volterra series. A FIR filter is used in the FW model as a feedback path to reproduce the PA memory effects. Also, a recursive identification algorithm based on the key-term separation principle is proposed and used for an experimental characterization of an LDMOS PA (50W–500MHz to 2.5GHz), with different carrier frequencies, bandwidths and output powers. The comparison with a conventional Generalized Memory Polynomial model (GMP) shows that the proposed model presents the same performances in term of behavioral modeling, with the advantage of a reduced number of parameters.

In this paper, we evaluate the effect of applying peak-to-average power ratio (PAPR) reduction and digital pre-distortion (DPD) on two types of radio frequency power amplifiers when an orthogonal frequency division multiplexing (OFDM) signal is used. The power amplifiers under test are a standard class-AB amplifier and a Doherty amplifier. The PAPR reduction methods are based on a state-of-the art convex optimization formulation and on the standard clipping and filtering technique. The DPD method consists of modeling the behavior of the power amplifier using a parallel Hammerstein model, and then extracting the inverse parameters based on the indirect learning architecture. To achieve better DPD performance, extracting the DPD parameters based on multiple-step iterations is investigated. The cases where PAPR reduction and DPD are applied separately and combined are studied and investigated. Power amplifier figures of merit are evaluated. Good performance is shown when combining both pre-processing techniques up to a certain operating point where DPD performance deteriorates due to generation of strong peaks in the signal. In addition, a difference in the power amplifier behavior is reported and analyzed.

In this paper, we present a low-power high-performance digital predistorter (DPD) for the linearization of wideband RF power amplifiers (PAs). It is based on the novel FIR memory polynomial (FIR-MP) predistorter model, which significantly augments the performance of the conventional memory polynomial predistorter with the use of complex baseband digital FIR filter prior to the memory polynomial. The adjacent channel leakage ratio (ACLR) performance comparison between the conventional MP and the proposed FIR-MP is done based on simulations with multi-carrier modulated signals of 20 and 80 MHz bandwidths. The PA models used for the simulations are extracted from the measurements of a commercial $$1\,\hbox {W}$$ GaAs HBT PA. At the ideal system-level simulations, the improvements in ACLR over the conventional MP are 7.2 and 15.6 dB, respectively, for 20 and 80 MHz signals. The choice of selection of various parameters of the predistorter along with the subsequent digital-to-analog converter (DAC) is presented. The impact of fixed-point representation is assessed using ACLR metrics, which shows that a wordlength of 14 bits is sufficient to obtain ACLR beyond $$45\,\hbox {dBc}$$ with a margin of $$10\,\hbox {dB}$$ . The proposed predistorter is synthesized in $$28\,\hbox {nm}$$ fully-depleted silicon-on-insulator (FDSOI) CMOS process. It is shown that with a fraction of the power and die area of that of the MP a huge improvement in ACLR is attained. With an overall power consumption of 8.2 and 88.8 mW, respectively, for 20 and 80 MHz signals, the FIR-MP DPD proves to be a suitable candidate for small-cell base station PA linearization.

A simplified memory polynomial (MP) behavioral model is proposed for single and dual band power amplifiers (PAs) modeling and digital predistorters (DPD). By integrating the quadratic component of the amplitude into conventional MPs, the nonlinearity orders and hence the complexity for model identification can be reduced effectively. The availability of the proposed single and dual band models are validated by computer simulation and experimental verification. Finally, a 10MHz long term evolution (LTE) modulated signal was tested on single-band model, experimental results show the proposed algorithm obtains around 20dB correction in adjacent channel power ratio (ACPR), which outperforms the conventional MP with the same nonlinear orders and achieves an ACPR improvement of 2.8dB.A forword modeling for dual-band PA is aslo implemented, and the normalized mean squared error (NMSE) in 1.9GHz and 2.4GHz improvement of 2.8dB and 3.5dB is achieved.

This article investigates the issue of low-cost digital predistortion (DPD) implementation in fixed-point field programmable gate array (FPGA) by considering the bit-resolution along with lower number of coefficients. The impact of principle component analysis (PCA) on bit-resolution of DPD solution is proposed within the context of established DPD models. Unlike previously proposed PCA based solutions, it is established by simulation and measurement that the numerical stability problem associated with popular models such as memory polynomial (MP) can be alleviated when PCA is applied to the observation data matrix. It is reported with measurement results that PCA based model provides better linearization performance with the least memory size requirement and number of LUTs in 16-bit fixed-point FPGA operation than MP, orthogonal memory polynomial (OMP), and generalized memory polynomial (GMP) models. The performance of the proposed model, is evaluated in terms of normalized mean square error, adjacent channel error power ratio, matrix condition number, and dispersion coefficient for continuous Class-AB and ZX60-V63+ power amplifiers using wide code-division multiple access signal (WCDMA) and long term evolution (LTE) signal with peak-to-average-power ratio (PAPR) around 9.895 and 11.92 dB, respectively.

This paper investigates the trade-off between power amplifier (PA) nonlinearity, output power backoff (OBO), digital predistortion (DPD), and clipping and filtering (CF) in terms of energy consumption. The energy efficiency of a PA depends on the OBO of the signal and usually increases as the OBO decreases. Peak to average power ratio (PAPR) reduction methods like CF and PA linearization algorithms like DPD methods allow the use of a smaller OBO. Those algorithms show best results when used together. By studying the trade-off between the power consumed in the CF and DPD circuits versus having a larger OBO for a target bit-error rate (BER), we show that below a certain PA output power the power consumption is not reduced by decreasing the OBO. We also show that the increase in distortion noise when using DPD and CF might defeat the purpose of their use in terms of power consumption. Given the trend toward smaller cells like femtocells, requiring less output power, CF and DPD may not be required at all, leading to a simpler and power saving transmitter design.

Digital predistortion (DPD) exploiting the Volterra series can effectively compensate the strong nonlinearities (with memory effects) of power amplifiers. Diverse pruning schemes have been proposed to reduce the computational complexity with comparative performances. Regrettably, the mechanism of basis construction in different DPDs that is related to the complexity-efficiency tradeoff has not been well-studied. In order to compare methodically the Volterra-series based DPDs, the key parameters of the basis are studied here. Especially for the cross terms that describe the interaction between nonlinearities and memory effect, the complexity-efficiency tradeoff cannot be addressed directly. Thus, the basis construction of DPDs is firstly mapped to the general Volterra-series to observe the pruning property of each DPD. The diagonal dispersal property on basis construction is concluded as the most efficient and reliable way for pruning DPD techniques. The running complexity-accuracy tradeoff is quantitatively analyzed via the number of floating point operations. With the best performance settings found by the Qhull algorithm, the experimental results show that (1) the nonlinear order of the cross terms is more significant than the related memory depth, and (2) basis construction with diagonal dispersal properties effectively shows the complexity-efficiency tradeoff of different DPDs. These results offer new angles to assess the feasibility of DPDs and their involved complexity.

This paper reports a novel digital predistortion (DPD) scheme for concurrent tri-band power amplifier (PA). The proposed three-dimensional tri-band DPD is based on the analysis of crosstalk between the fundamental frequencies, their harmonics and intermodulation products due to the nonlinearity exhibited by the tri-band PA. The DPD performance is validated using a broadband PA driven concurrently with LTE, WIMAX, and WCDMA signals centered at 2.14 GHz, 2.425 GHz, and 2.655 GHz, respectively.

<span lang="EN-US">In this paper, a low-complexity model is proposed for linearizing power amplifiers with memory effects using the digital predistortion (DPD) technique. In the proposed model, the linear, low-order nonlinear and high-order nonlinear memory effects are computed separately to provide flexibility in controlling the model parameters so that both high performance and low model complexity can be achieved. The performance of the proposed model is assessed based on experimental measurements of a commercial class AB power amplifier by applying a single-carrier wideband code division multiple access (WCDMA) signal. The linearity performance and the model complexity of the proposed model are compared with the memory polynomial (MP) model and the DPD with single-feedback model. The experimental results show that the proposed model outperforms the latter model by 5 dB in terms of adjacent channel leakage power ratio (ACLR) with comparable complexity. Compared to MP model, the proposed model shows improved ACLR performance by 10.8 dB with a reduction in the complexity by 17% in terms of number of floating-point operations (FLOPs) and 18% in terms of number of model coefficients.</span>

This paper deals with Field Programmable Gate Array (FPGA) implementation design of a Predistorter real-time processing. The corresponding Baseband Digital Predistortion (DPD) is based on Memory Polynomial (MP) modelling of a UHF 8 MHz LDMOS Power Amplifier (PA). The PA MP model coefficients are estimated based on Least Square Estimation (LSE) algorithm. The proposed DPD design is using Look Up Table (LUT) for the Predistorter unit and the Indirect Learning Architecture (ILA) approach for estimating the coefficients of the predistorter. Implementation test results for the UHF LDMOS PA with DVB-T modulated signals showed good linearization performances with the adjacent channel power ratio (ACPR) reaching −46 dB.

Theoretically, memoryless nonlinear effect is the main concern for RF power amplifier (PA) modelling and analysis. However, the latest generation wireless communication systems, such as Wi-Fi, WiMAX and LTE, using wider bandwidth, add new problems for the analysis of RF PAs, which is the memory effect associated with the bandwidth. The memory effect causes additional distortion to the PA and affects the performance of digital predistortion (DPD) design. Previously, we predicted the memoryless spectrum regrowth of a PA related to its intercept points up to arbitrary high order for a few of wireless communication signals, such as TDMA, CMDA and OFDM. In this letter, we propose a simplified Hammerstein structure-based method to consider the memory effect as well in order to analyse the nonlinear characteristic of PAs more precisely and completely. The simplification greatly reduced the complexity of classic Hammerstein system identification for PAs. The result will be useful in the analysis of RF PAs with memory effect and the proposed PA model is intended to be used in predistorter design for modern wideband wireless communication systems.

The application of digital predistortion in base band signal is an extended method of amplifier linearization to reduce the adjacent channel interference (ACI) in those systems in which a varying envelope modulation scheme like OFDM and MQAM is used. Digital baseband predistortion is a highly cost-effective way to linearize power amplifiers (PAs), but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored. In this paper we proposed a new technique for adaptation of digital predistorter that considers memory effects in power amplifiers. This method is a combination of two techniques, memory polynomial predistortion and slope-dependent method. This new technique is validated by using a 1.9 GHz 60W LDMOS power amplifier and various signals such as 2-carrier and 3-carrier CDMA.