Performance analysis of multi-stage cascaded digital predistortion

In this paper, a new model which is called a pruning general memory polynomial (PGMP) model is introduced to solve the conflict between model precision and complexity in DPD research. The new model eliminates those items which have little effect to output signal from the expression of the traditional general memory polynomial (GMP) and obtain a new model expression which has similar performance with the PGMP model and similar coefficient number with the memory polynomial model. The experiment result shows that the new DPD model exhibits a very good performance and its ACPR of output spectrum is 5dB better than that of MP model.

In this paper, a novel multi-band reduced sampling rate technique is proposed for power amplifier (PA) linearization system. It is used to enhance performance and reduce hardware costs in spectrum aggregation discontinuous broadband systems and compensate in-phase/quadrature (I/Q) imbalance in the multi-band case. During the feedback loop process of sampling rate, a band-limited filter is introduced, and the frequency band extrapolation is carried out so that the spectrum outside the limited band is compensated effectively. Theoretical analysis is performed to compare the proposed method and the conventional methods. To evaluate the performance of the proposed method, a broadband PA is excited by a tri-band signal composed of a 20 MHz long-term evolution (LTE) signal at 1.31 GHz, a 20 MHz 4-carrier wideband code division multiple access (WCDMA) signal at 2.49 GHz, and a 20 MHz 2-carrier WiMAX signal at 2.58 GHz respectively. The experimental results demonstrate that the normalized mean square error (NMSE) can get high accuracy less than −41 dB, with peak-to-average power ratio (PAPR) equaling 9 dB accompanied by a large reduction in sampling rate. Error vector magnitude (EVM) is 1% better than band-limited memory polynomial (MP) model and 2.3% better than conventional MP model.

This article investigates the issue of low-cost digital predistortion (DPD) implementation in fixed-point field programmable gate array (FPGA) by considering the bit-resolution along with lower number of coefficients. The impact of principle component analysis (PCA) on bit-resolution of DPD solution is proposed within the context of established DPD models. Unlike previously proposed PCA based solutions, it is established by simulation and measurement that the numerical stability problem associated with popular models such as memory polynomial (MP) can be alleviated when PCA is applied to the observation data matrix. It is reported with measurement results that PCA based model provides better linearization performance with the least memory size requirement and number of LUTs in 16-bit fixed-point FPGA operation than MP, orthogonal memory polynomial (OMP), and generalized memory polynomial (GMP) models. The performance of the proposed model, is evaluated in terms of normalized mean square error, adjacent channel error power ratio, matrix condition number, and dispersion coefficient for continuous Class-AB and ZX60-V63+ power amplifiers using wide code-division multiple access signal (WCDMA) and long term evolution (LTE) signal with peak-to-average-power ratio (PAPR) around 9.895 and 11.92 dB, respectively.

A Baseband Digital Predistorter design is proposed in this paper for a UHF 8 MHz Power Amplifier (PA) for DVB-T transmitter. A Memory Polynomial (MP) model is considered for the PA characterization and its coefficients are estimated based on Least Square Estimation (LSE) algorithm. The Indirect Learning Architecture (ILA) approach is used to estimate the coefficients of the predistorter. Simulation and FPGA implementation tests hase been carried out by using measured input/output samples of a 110 W Class AB UHF LDMOS PA. Test results showed an improvement of 21 dB in Adjacent Channel Power Ratio (ACPR) and the Normalized Mean Square Error (NMSE) reached −56 dB.

Research on digital predistortion technique of harmonic cancellation based on volterra series

This paper presents the black-box modeling of a microwave power amplifier (PA) operating near saturation and the performance of a modular predistortion model designed for this PA. A 16-QAM modulation scheme has been used as input signal. Nonlinearities caused by the amplifier operating at low input back-off (IBO), that is close to compression, can change the output constellation and lead to difficulties in finding the correct model parameters since the black-box identification procedure is based on measured input/output signals. A segment of the input/output measurement data is processed to generate an initial model. Then pseudo-inverse techniques are used to find a parsimonious Wiener model that is cross-validated with the entire measurement data. The presented modeling approach results in a model intended to be numerically robust and having a high identification percentage based on the normalized mean squared error (NMSE) figure of merit. Once the PA model is obtained, a Hammerstein based predistorter (HPD) is estimated by means of the indirect learning approach (PA input-output measured data). Simulation and experimental results are provided in order to show linearity improvement achieved by this HPD. In band and out of band distortion compensation are measured in terms of adjacent channel power ratio (ACPR) and error vector magnitude (EVM) reduction.

An E-GPRS power amplifier controller, designed in a 5 V 0.5 /spl mu/m CMOS technology, is presented. Based on an open-loop polar modulation transmitter strategy for both GMSK in GSM and 8PSK in EDGE, the power control for both ramping and modulation depth is provided from collector supply control, and critical power amplifier (PA) temperature and process variability is compensated through the use of an automated bias calibration procedure detailed herein. Leveraging the architecture's capability for removal of transmit SAW filters, removal of isolators and maintenance of critical adjacent channel power ratio (ACPR) and error vector magnitude (EVM) performance into PA output mismatched impedance environments, the controller provides excellent linearity for higher power 8PSK power, and performance of transient spectrum due to switching even when run into the battery headroom limit of the supply rail.

Digital predistortion (DPD) technique is an effective means to alleviate the nonlinearity of power amplifiers (PAs) and improve transmitter efficiency. However, for orthogonal frequency division multiplexing (OFDM) systems with a high peak-to-average power ratio (PAPR), the PAPR reduction needs to be deployed in combination with DPD, to maximize transmitter efficiency. The extra complexity caused by the introduction of PAPR reduction on the main road has become a non-negligible defect. To address this issue, this letter proposes a joint PAPR reduction and DPD model based on the generalized memory polynomial (GMP). To train the joint GMP model, this letter improves the ping-pong joint optimization (P2JO) approach under the offline case, to obtain accurate training data. The comparative experimental results based on 100-MHz Doherty PA show that the proposed joint model significantly reduces the model complexity on the main road, while ensuring adjacent channel power ratio (ACPR) and bit error rate (BER).

The frequency and spatial characteristics of nonlin-ear distortion from a MIMO-OFDM (multiple-input multiple-output orthogonal frequency-division multiplexing) basestation with memoryful nonlinear amplifiers (modeled by a generalized memory polynomial) is studied herein. We prove a theorem about a linear representation of the amplified signal from which the nonlinear distortion is obtained. Our measurement results demonstrate that the generalized memory polynomial can provide better accuracy of the nonlinear distortion than the memoryless and memory polynomial models. Furthermore, it is shown that in contrast to the memoryless amplifier, the amplifier with memory can distort the useful linear signal and introduce interference in a wider range of sub carriers. The derived theory is useful to predict how the nonlinear distortion will behave, to analyze the in-band and out-of-band radiation, and to schedule users in the frequency plane to minimize the effect of nonlinear distortion.

Power amplifier (PA) behaviour modelling is a crucial technique for the improvement of telecommunication systems because it constitutes the core of a linearisation circuit that allows for the amplifier to develop high efficiencies at the same time that it delivers a linear output signal to the load. Polynomial filters can be used in order to represent both the non-linearities of the PA and the memory effects caused by passive elements of the circuit. This work proposes a different structure for a PA polynomial behaviour model, using finite impulse response (FIR) filters and one-dimensional polynomials. The memory polynomial (MP) and the envelope memory polynomial (EMP) models were used not only as a foundation for the proposed model but also as references points for performance validation. All models were applied to a class AB GaN PA driven by a WCDMA envelope signal. Results shown an enhancement on performance for the proposed model when its accuracy was compared with the one obtained by the MP and EMP models. In contrast with the first one, the proposed model had an improvement of 4.1 dB in its normalized mean square error (NMSE), with the second one, the improvement was of 5.9 dB.

A simplified memory polynomial (MP) behavioral model is proposed for single and dual band power amplifiers (PAs) modeling and digital predistorters (DPD). By integrating the quadratic component of the amplitude into conventional MPs, the nonlinearity orders and hence the complexity for model identification can be reduced effectively. The availability of the proposed single and dual band models are validated by computer simulation and experimental verification. Finally, a 10MHz long term evolution (LTE) modulated signal was tested on single-band model, experimental results show the proposed algorithm obtains around 20dB correction in adjacent channel power ratio (ACPR), which outperforms the conventional MP with the same nonlinear orders and achieves an ACPR improvement of 2.8dB.A forword modeling for dual-band PA is aslo implemented, and the normalized mean squared error (NMSE) in 1.9GHz and 2.4GHz improvement of 2.8dB and 3.5dB is achieved.

This paper deals with Field Programmable Gate Array (FPGA) implementation design of a Predistorter real-time processing. The corresponding Baseband Digital Predistortion (DPD) is based on Memory Polynomial (MP) modelling of a UHF 8 MHz LDMOS Power Amplifier (PA). The PA MP model coefficients are estimated based on Least Square Estimation (LSE) algorithm. The proposed DPD design is using Look Up Table (LUT) for the Predistorter unit and the Indirect Learning Architecture (ILA) approach for estimating the coefficients of the predistorter. Implementation test results for the UHF LDMOS PA with DVB-T modulated signals showed good linearization performances with the adjacent channel power ratio (ACPR) reaching −46 dB.

This paper proposes a Real-Valued Time-Delay Recurrent Radial Basis Function (RVTDRRBF) model suitable for dynamic modeling of the strongly nonlinear behaviors of the Doherty Power Amplifiers (DPAs). This model has four Tapped Delay Lines (TDLs), which account for the memory effect of the DPA. The structure of the RVTDRRBF model is simpler than the traditional FeedForward Neural Networks (FFNNs) model. Weights and centers of the proposed model can be resolved by the Orthogonal Least Square (OLS) and Singular Value De-composition (SVD) algorithm. A three-carrier Wideband Code Division Multiple Access (WCDMA) signal is taken as the test signal. The simulation results in frequency-domain and time-domain for a DPA with 51 dBm output illustrate a good agreement between the RVTDRRBF model and measurement data. Moreover, comparing the Normalized Mean Square Error (NMSE) of RVTDRRBF model, memory polynomial model and RVTDRBF model, it can be noticed that the proposed RVTDRRBF model is more accurate than the RVTDRBF model and the memory polynomial model in modeling the strong dynamic nonlinearity of the DPAs.

New mobile applications require the use of Radio Frequency Power Amplifiers (RF PA) in a context of reconfigurability and adaptability. In this paper, we propose a modeling study of RF PA in this context. The proposed approach is a combination of a Feedback-Wiener (FW) structure with a Memory Polynomial (MP) model, which gives a pruned Volterra series. A FIR filter is used in the FW model as a feedback path to reproduce the PA memory effects. Also, a recursive identification algorithm based on the key-term separation principle is proposed and used for an experimental characterization of an LDMOS PA (50W–500MHz to 2.5GHz), with different carrier frequencies, bandwidths and output powers. The comparison with a conventional Generalized Memory Polynomial model (GMP) shows that the proposed model presents the same performances in term of behavioral modeling, with the advantage of a reduced number of parameters.

We have demonstrated a frequency multiplier-based multiplying transmitter (MT) architecture, which shows the transmission of wideband modulated signals from the lower frequency band to the millimeter-wave (mm-wave) through the frequency multiplier directly is a viable option. To compensate for the severe nonlinear distortions exhibited by the frequency multiplier in a more efficient way, a two-stage cascaded digital predistortion (DPD) scheme with constrained feedback bandwidth is proposed. The complexity-reduced generalized memory polynomial (GMP) and $N$ th-order power/root module are used for nonlinear behavioral modeling. Furthermore, the spectral extrapolation and band-divided (BD) modeling methods are employed to achieve more accurate linearization performance of the frequency multiplier over the limited feedback bandwidth. The MT experimental system with an active frequency quadrupler at the Q-band was set up to evaluate the linearization capacity of the proposed BD $N$ th-order cascaded complexity-reduced GMP (BD-N-CGMP) DPD scheme. In the test for 24-MHz bandwidth 16 quadrature amplitude modulation (QAM) signal, the frequency quadrupler’s linearized output at 48.6 GHz with error vector magnitude (EVM) of 1.94% and adjacent channel power ratio (ACPR) of −47.2 dBc could be achieved, even when the feedback bandwidth was limited from 480 to 78 MHz. This demonstrated system significantly decreased the requirement of the digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) sampling rate, and showed promising performances for future MT architecture at mm-wave and sub-terahertz (sub-THz) frequencies with large signal bandwidth.