An adaptive memory management protocol for Time Warp parallel simulation

Global virtual time (GVT) is used in the Time Warp synchronization mechanism to perform irrevocable operations such as I/O and to reclaim storage. Most existing algorithms for computing GVT assume a message-passing programming model. Here, GVT computation is examined in the context of a shared-memory model. We observe that computation of GVT is much simpler in shared-memory multiprocessors because these machines normally guarantee that no two processors will observe a set of memory operations as occurring in different orders. Exploiting this fact, we propose an efficient, asynchronous, shared-memory GVT algorithm and prove its correctness. This algorithm does not require message acknowledgments, special GVT messages, or FIFO delivery of messages, and requires only a minimal number of shared variables and data structures. The algorithm only requires one round of interprocessor communication to compute GVT, in contrast to many message-based algorithms that require two. An efficient implementatin is described that eliminates the need for a processor to explicitly compute a local minimum for time warp systems using a lowest-timestamp-first scheduling policy in each processor. In addition, we propose a new mechanism called on-the-fly fossil collection that enables efficient storage reclamation for simulations containing large numbers, e.g., hundreds of thousand or even millions of simulator objects. On-the-fly fossil collection can be used in time warp systems executing on either shared-memory or message-based machines. Performance measurements of the GVT algorithm and the on-the-fly fossil collection mechanism on a Kendall Square Research KSR-2 machine demonstrate that these techniques enable frequent GVT and fossil collections, e.g., every millisecond, without incurring a significant performance penalty

Optimism is a technique used by the Time Warp paradigm to make decisions about event execution under uncertainty. While the benefits of throttling the optimism of Time Warp has been studied, the benefits of extending optimism to operations besides event execution is presented in this paper. Specifically, we discuss how optimism can be mapped to fossil collection which has traditionally been assumed to be a non-recoverable operation that must be performed under global control. Optimistic Fossil Collection (OFC) is a technique for fossil collection that does not require global control. However, as states are fossil collected optimistically, a recovery mechanism is required to recover from errors. Performance results show that Time Warp using OFC can improve the performance of simulations on a network of workstations. Another benefit of OFC is that the simulation checkpoints provide for fault tolerance in more than just fossil collection.

Mechanisms for managing message buffers in Time Warp parallel simulations executing on cache-coherent shared-memory multiprocessors are studied. Two simple buffer management strategies called the sender pool and receiver pool mechanisms are examined with respect to their efficiency, and in particular, their interaction with multiprocessor cache-coherence protocols. Measurements of implementations on a Kendall Square Research KSR-2 machine using both synthetic workloads and benchmark applications demonstrate that sender pools offer significant performance advantages over receiver pools. However, it is also observed that both schemes, especially the sender pool mechanism, are prone to severe performance degradations due to poor locality of reference in large simulations using substantial amounts of message buffer memory. A third strategy called the partitioned buffer pool approach is proposed that exploits the advantages of sender pools, but exhibits much better locality. Measurements of this approach indicate that the partitioned pool mechanism yields substantially better performance than both the sender and receiver pool schemes for large-scale, small-granularity parallel simulation applications. The central conclusions from this study are: (1) buffer management strategies play an important role in determining the overall efficiency of multiprocessor-based parallel simulators, and (2) the partitioned buffer pool organization offers significantly better performance than the sender and receiver pool schemes. These studies demonstrate that poor performance may result if proper attention is not paid to realizing an efficient buffer management mechanism.

We describe SsQueue(SnapshotQueue), an implementation for an efficient and user-friendly class library for FIFO queue that can be used for state vectors in simulated queuing network constructs under Time Warp parallel discrete event simulation (PDES) protocol. There exists a general purpose Time Warp simulation kernel warped, where users have only to define a state vector and do not have to care about rollback and state recovery. However, since the state vector should be defined as an inlined data structure, it is not suitable for dynamic data structures such as FIFO queue. This class can also serve as an element of such a state vector, then both libraries and users can handle each instance as snapshot of the queue. Taking advantages of FCFS nature of the above data structure, operation histories rather than all contained items can be safely stored and restored using this class library with virtually minimum overhead. When the kernel deletes instances in the simulated past, corresponding methods perform garbage collections transparently.

The exponential increase in multicore processor (CMP) cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with a single, uniform access latency. Non-Uniform Cache Architecture (NUCA) designs have been proposed to address this problem. A NUCA divides the whole cache memory into smaller banks and allows banks nearer a processor core to have lower access latencies than those further away, thus mitigating the effects of the cache's internal wires. Determining the best placement for data in the NUCA cache at any particular moment during program execution is crucial for exploiting the benefits that this architecture provides. Dynamic NUCA (D-NUCA) allows data to be mapped to multiple banks within the NUCA cache, and then uses data migration to adapt data placement to the program's behavior. Although the standard migration scheme is effective in moving data to its optimal position within the cache, half the hits still occur within non-optimal banks. This paper reduces this number by anticipating data migrations and moving data to the optimal banks in advance of being required. We introduce a prefetcher component to the NUCA cache that predicts the next memory request based on the past. We develop a realistic implementation of this prefetcher and, furthermore, experiment with a perfect prefetcher that always knows where the data resides, in order to evaluate the limits of this approach. We show that using our realistic data prefetching to anticipate data migrations in the NUCA cache can reduce the access latency by 15% on average and achieve performance improvements of up to 17%.

This paper compares the performance of executing compiled Prolog code on two different architectures under development at U. C. Berkeley. The first is the PLM, a special-purpose CISC architecture intended as a coprocessor for a host machine. The second is SPUR, a general-purpose RISC architecture that supports tagged data. Fourteen standard benchmark programs were run on both the PLM and SPUR simulators. The compiled code for SPUR was obtained by simple macro-expansion of PLM code generated by the PLM Prolog compiler. The two implementations are compared with regard to static and dynamic program size, execution speed, and memory system performance. On average, the macrocoded SPUR implementation has a static code size 14 times larger than the PLM, executes 16 times more instructions, yet requires only 2.3 times the number of machine cycles (or has the performance of 0.43 PLMs). When memory system performance is taken into account, SPUR is equivalent to 0.29 PLMs. Optimizations of the macro-expanded code and minor architectural changes to SPUR would increase this ratio to 0.53, or 0.60 for the largest benchmarks. Thus a tagged RISC architecture can execute Prolog at least half as fast as a special-purpose CISC architecture for Prolog.

Accurately predicting program behaviors (e.g., memory locality, method calling frequency) is fundamental for program optimizations and runtime adaptations. Despite decades of remarkable progress, prior studies have not systematically exploited the use of program inputs, a deciding factor of program behaviors, to help in program dynamic optimizations. Triggered by the strong and predictive correlations between program inputs and program behaviors that recent studies have uncovered, the dissertation work aims to bring program inputs into the focus of program behavior analysis and program dynamic optimization, cultivating a new paradigm named input-centric program behavior analysis and dynamic optimization.;The new optimization paradigm consists of three components, forming a three-layer pyramid. at the base is program input characterization, a component for resolving the complexity in program raw inputs and extracting important features. In the middle is input-behavior modeling, a component for recognizing and modeling the correlations between characterized input features and program behaviors. These two components constitute input-centric program behavior analysis, which (ideally) is able to predict the large-scope behaviors of a program's execution as soon as the execution starts. The top layer is input-centric adaptation, which capitalizes on the novel opportunities created by the first two components to facilitate proactive adaptation for program optimizations.;This dissertation aims to develop this paradigm in two stages. In the first stage, we concentrate on exploring the implications of program inputs for program behaviors and dynamic optimization. We construct the basic input-centric optimization framework based on of line training to realize the basic functionalities of the three major components of the paradigm. For the second stage, we focus on making the paradigm practical by addressing multi-facet issues in handling input complexities, transparent training data collection, predictive model evolvement across production runs. The techniques proposed in this stage together cultivate a lifelong continuous optimization scheme with cross-input adaptivity.;Fundamentally the new optimization paradigm provides a brand new solution for program dynamic optimization. The techniques proposed in the dissertation together resolve the adaptivity-proactivity dilemma that has been limiting the effectiveness of existing optimization techniques. its benefits are demonstrated through proactive dynamic optimizations in Jikes RVM and version selection using IBM XL C Compiler, yielding significant performance improvement on a set of Java and C/C++ programs. It may open new opportunities for a broad range of runtime optimizations and adaptations. The evaluation results on both Java and C/C++ applications demonstrate the new paradigm is promising in advancing the current state of program optimizations.

Locality of reference in program behavior has been studied and modelled extensively because of its application to CPU, cache and virtual memory design, code optimization, multiprogramming etc. In this paper we propose a scheme based on Markov chains for modelling the time interval between successive references to the same address in a program execution. Using this technique and trace driven simulations, it is shown that memory references are predictable and repetitive. This is used to improve miss ratios of memory replacement algorithms. Using trace driven simulations over a wide range of traces we get improvements up to 35% over the least recently used (LRU) replacement algorithm. >

This work presents an unsupervised approach for visualizing, analyzing, and monitoring large multivariate time series data in lower-dimensional spaces. The method integrates dynamic time warping (DTW) with graph-based layout algorithms to uncover temporal structure and similarity across complex data sets─without requiring labeled data or predefined models. It works by segmenting time series into windows and computing pairwise DTW distances to capture the temporal alignment. These distances are then used to construct a k-nearest neighbor (k-NN) graph, which is visualized by using a force-directed layout algorithm. The resulting map offers an interpretable representation of the time series structure, where the spatial proximity corresponds to the temporal similarity between data windows. Unlike traditional dimensionality reduction (DR) techniques, this method does not project data into feature space; instead, it visualizes the relational topology of DTW-aligned patterns. This provides a powerful and intuitive tool for revealing the structure in complex temporal data. The framework also supports online monitoring with an adaptive threshold mechanism for real-time anomaly detection.

Program behaviour characteristics were examined using data gathered from real program executions. Experiments were performed in a segmented virtual memory with a working set policy; the analyzing costs were kept low using an efficient data reduction method. Empirical results were obtained concerning the influence of the window size on program behaviour characteristics, the accuracy of some average working set size approximations and the sensitivity of program behaviour to the program's input data. These results show that some commonly used assumptions concerning program behaviour are inaccurate. Also there seem to exist “ill-behaving” programs, the behaviour of which does not correspond well with results obtained earlier. The effects of real-time delays during program execution were considered using a new simple method. As an additional experiment, segmenting and paging were compared using various performance statistics; the results seem to favour segmenting.

Developing fast chip multiprocessor simulation techniques is a challenging problem. Solving this problem is especially valuable for design space exploration purposes during the early stages of the design cycle where a large number of design points need to be evaluated quickly. This paper studies statistical simulation as a fast simulation technique for chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to measure a number of program execution characteristics from a real program execution through profiling, to generate a synthetic trace from it, and simulate that synthetic trace as a proxy for the original program. The important benefit is that the synthetic trace is much shorter compared to a real program trace, which leads to substantial simulation speedups. This paper enhances state-of-the-art statistical simulation: 1) by modeling the memory address stream behavior in a more microarchitecture-independent way and 2) by modeling a program's time-varying execution behavior. These two enhancements enable accurately modeling resource conflicts in shared resources as observed in the memory hierarchy of contemporary chip multiprocessors when multiple programs are coexecuting on the CMP. Our experimental evaluation using the SPEC CPU benchmarks demonstrates average prediction error of 7.3 percent across a range of CMP configurations while varying the number of cores and memory hierarchy configurations.

Economic transformations of the country due to the development of market relations lead to appropriate changes in the field of social policy, the development of appropriate mechanisms of social protection, based on the principles of self-regulation and mutual support. The scale of economic growth is largely determined by the level of motivation of the behavior of economic entities both in increasing their own financial results and the general economic effect of creating a social product. In this aspect, the social policy of the state becomes a powerful factor in economic growth, with the greatest effect is given by the use of such forms of incentives that realize the public interests of all economic entities, which are not homogeneous in nature. The implementation of these priorities should be aimed at solving major socio-economic problems in order to prevent conflicts and promote sustainable development at the level of enterprises, regions, the country as a whole, so the problem of harmonizing the interests of all economic entities can be identified as a priority. The urgency of this problem is due to the need to increase the level of social protection of the population, which is achieved through the effective implementation of social policy and improving the mechanisms for its implementation from the standpoint of harmonization of interests of all economic entities. It is proved that to form a low-conflict model in which each entity has a clearly defined mechanism for meeting their own needs through the interests of partners, possibly by expanding the scope of market methods of self-regulation in combination with government leverage to influence economic behavior. To implement a more effective social policy, the government proposed a mechanism for expanding and harmonizing the socio-economic interests of the state, business and employees, which summarizes the result of the synthesis of natural and artificial responsibilities for various actors in social policy and social partnership. The proposed mechanism is able to neutralize the problems associated with low wages in the real sector of the economy, poverty and inefficient use of GDP, ensure the transparency of this process, and create a powerful motivational environment for workers and employers.

Embedded system security is often compromised when "trusted" software is subverted to result in unintended behavior, such as leakage of sensitive data or execution of malicious code. Several countermeasures have been proposed in the literature to counteract these intrusions. A common underlying theme in most of them is to define security policies at the system level in an application-independent manner and check for security violations either statically or at run time. In this paper, we present a methodology that addresses this issue from a different perspective. It defines correct execution as synonymous with the way the program was intended to run and employs a dedicated hardware monitor to detect and prevent unintended program behavior. Specifically, we extract properties of an embedded program through static program analysis and use them as the bases for enforcing permissible program behavior at run time. The processor architecture is augmented with a hardware monitor that observes the program's dynamic execution trace, checks whether it falls within the allowed program behavior, and flags any deviations from expected behavior to trigger appropriate response mechanisms. We present properties that capture permissible program behavior at different levels of granularity, namely inter-procedural control flow, intra-procedural control flow, and instruction-stream integrity. We outline a systematic methodology to design application-specific hardware monitors for any given embedded program. Hardware implementations using a commercial design flow, and cycle-accurate performance simulations indicate that the proposed technique can thwart several common software and physical attacks, facilitating secure program execution with minimal overheads

This paper proposes an adaptive slot allocation mechanism to improve the performance of Transmission Control Protocol (TCP) in DOCSIS-based hybrid fiber coaxial (HFC) networks. The proposed mechanism is comprised of two parts: fast request transmission (FRT) and long packet deferment (LPD). FRT is designed to handle TCP transfers, while LDP targets transfers. Here one-way transfers means all active cable modems perform downloading; while two-way transfers indicates some perform downloading and some perform uploading. We analyze the proposed mechanism and conduct simulations using network simulator ns-2 to evaluate the performance of our mechanism. The results show that the proposed mechanism has better performance in terms of aggregate downstream throughput, access delay, and required buffer size, as compared to the original control mechanism of DOCSIS.

The Hypertext Transfer Protocol (HTTP) Adaptive Streaming (HAS) has now become ubiquitous and accounts for a large amount of video delivery over the Internet. But since the Internet is prone to bandwidth variations, HAS's up and down switching between different video bitrates to keep up with bandwidth variations leads to a reduction in Quality of Experience (QoE). In this article, we propose a video bitrate adaptation and prediction mechanism based on Fuzzy logic for HAS players, which takes into consideration the estimate of available network bandwidth as well as the predicted buffer occupancy level in order to proactively and intelligently respond to current conditions. This leads to two contributions: First, it allows HAS players to take appropriate actions, sooner than existing methods, to prevent playback interruptions caused by buffer underrun, reducing the ON-OFF traffic phenomena associated with current approaches and increasing the QoE. Second, it facilitates fair sharing of bandwidth among competing players at the bottleneck link. We present the implementation of our proposed mechanism and provide both empirical/QoE analysis and performance comparison with existing work. Our results show that, compared to existing systems, our system has (1) better fairness among multiple competing players by almost 50% on average and as much as 80% as indicated by Jain's fairness index and (2) better perceived quality of video by almost 8% on average and as much as 17%, according to the estimate the Mean Opinion Score (eMOS) model.