An adaptive-method for velocity estimation using time-to-digital converter

Improving timing resolution in positron emission tomography (PET), thus having fine time information of the detected pulses, is important to increase the reconstructed images signal to noise ratio (SNR) [1]. In the present work, an integrated circuit topology for time extraction of the incoming pulses is evaluated. An accurate simulation including the detector physics and the electronics with different configurations has been developed. The selected architecture is intended for a PET system based on a continuous scintillation crystal attached to a SiPM array. The integrated circuit extracts the time stamp from the first few photons generated when the gamma-ray interacts with the scintillator, thus obtaining the best time resolution. To get the time stamp from the detected pulses, a time to digital converter (TDC) array based architecture has been proposed as in [2] or [3]. The TDC input stage uses a current comparator to transform the analog signal into a digital signal. Individually configurable trigger levels allow us to avoid false triggers due to signal noise. Using a TDC per SiPM configuration results in a very area consuming integrated circuit. One solution to this problem is to join several SiPM outputs to one TDC. This reduces the number of TDCs but, on the other hand, the first photons will be more difficult to be detected. For this reason, it is important to simulate how the time resolution is degraded when the number of TDCs is reduced. Following this criteria, the best configuration will be selected considering the trade-off between achievable time resolution and the cost per chip. A simulation is presented that uses Geant4 for simulation of the physics process and, for the electronic blocks, spice and Matlab. The Geant4 stage simulates the gamma-ray interaction with the scintillator, the photon shower generation and the first stages of the SiPM. The electronics simulation includes an electrical model of the SiPM array and all the integrated circuitry that generates the time stamps. Time resolution results are analyzed using Matlab. The goal is to analyze the best resolution achievable with the SiPM and its degradation due to different circuitry configurations.

This work proposed a new time-to-digital converter (TDC) utilizing rapid single-flux-quantum circuits. The proposed TDC architecture comprises a counter and a ring oscillator to construct a coarse TDC and a vernier delay line to build a fine TDC, which would maintain the high resolution and high dynamic range of the whole TDC. A TDC with the proposed architecture has been designed, fabricated, and successfully tested. The measurement shows that the designed TDC works correctly with a 5.5 ps resolution, a 1320 ps dynamic range, and a 1.5 LSB differential nonlinearity.

Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning, a self-calibration method is proposed, which allows for the calibration after the tape-out. The method utilizes a ruler DTC(RDTC) as the input signal of TDC to calibrate it. After self-calibration, the resolution of TDC is equal to the RDTC's delay step, so the resolution becomes adjustable by altering the RDTC's delay step. Setting the resolution at 1ps, the integral nonlinearity (INL) is 0.07LSB, the power consumption is 1.37mW at 50MHz with a 1.2V operating voltage and it occupies a core area of 0.018 mm2 in 0.13um CMOS process.

This paper proposes an ultra wide input time interval range, two-step (TS) time-to-digital converter (TDC) with a foreground coarse gain calibration. The proposed TS TDC converts the input time intervals by sequentially using two TDCs that have different dynamic ranges and time resolutions. The fine 2nd stage incorporates a pulse-shrinking ring architecture to achieve sub-gate-delay resolution, whereas the coarse 1st stage uses a simple ring-oscillator-based TDC. The time resolution of the 1st stage is foreground-calibrated at start-up by utilizing the fine 2nd stage TDC. The TDC simulated in a 0.18 pm standard CMOS technology demonstrates 1.8 ps resolution and 16 bit range that corresponds to 118 ns input time interval with 0.07 mm2 area. It operates at 3.3 MS/s with 12.7 mW, and achieves 1.28 ps single-shot precision.

In this paper, a novel in-pixel time-to-digital converter (TDC) for 3D time-of-flight cameras is presented. Coarse---fine architecture has been used to guarantee both wide dynamic range and high time resolution. The proposed TDC exploits pulse-train time amplifier (TA) to further improve the time resolution and optimize time error performance. The 11-bit TDC provides 62.5 ps resolution and 126 ns full-scale range. Simulation results indicate the TDC achieves a DNL of under 0.52 LSB and INL less than 0.8 LSB. Both the TA and TDC are designed in GSMC CIS 0.18 μm 1P6M technology.

We propose a gain estimation technique of a digital-to-time converter (DTC) and a time-to-digital converter (TDC) intended for an all-digital phase-locked loop (ADPLL) that is based on a recently introduced phase-prediction (PP) technique. Such a PP-ADPLL reduces the timing range and thus complexity of the fractional part of the phase detection mechanism. The conventional TDC gain estimation methods based on measuring the DCO clock period are not feasible for PP-ADPLLs due to the TDC timing range being much smaller than one DCO clock period. The proposed gain estimation method can run concurrently with the normal ADPLL phase locking process and its feasibility is confirmed through behavioral simulations. Although the estimation method is specifically proposed for the PP-ADPLL, its operating principle can also be applied to conventional ADPLL architectures that require an accurate TDC gain estimation.

Vision-based ego-velocity estimation is a fundamental problem in robot state estimation. However, the constraints of frame-based cameras, including motion blur and insufficient frame rates in dynamic settings, readily lead to the failure of conventional velocity estimation techniques. Mammals exhibit a remarkable ability to accurately estimate their ego-velocity during aggressive movement. Hence, integrating this capability into robots shows great promise for addressing these challenges. In this letter, we propose a brain-inspired framework for linear-angular velocity estimation, dubbed NeuroVE. The NeuroVE framework employs an event camera to capture the motion information and implements spiking neural networks (SNNs) to simulate the brain's spatial cells' function for velocity estimation. We formulate the velocity estimation as a time-series forecasting problem. To this end, we design an Astrocyte Leaky Integrate-and-Fire (ALIF) neuron model to encode continuous values. Additionally, we have developed an Astrocyte Spiking Long Short-term Memory (ASLSTM) structure, which significantly improves the time-series forecasting capabilities, enabling an accurate estimate of ego-velocity. Results from both simulation and real-world experiments indicate that NeuroVE has achieved an approximate 60% increase in accuracy compared to other SNN-based approaches.

Phase locked loops (PLLs) are utilized in SoCs for automotive industry. In the industry, the system handles with satellite signals which are weak radio waves coming from space. Therefore, the output frequency of PLLs is carefully designed to avoid Electromagnetic Interference (EMI). Recently, Global Navigation Satellite System (GNSS) is becoming more common and available frequency bands for clocks are getting narrow (Fig. 1 (a)). That leads, in many products, replacement integer-N PLLs (Int-N PLLs) with fractional-N PLLs (Frac-N PLLs) is needed to obtain smaller output frequency steps than reference frequency. It is important to make Frac-N PLLs as soon as possible to meet a market opportunity. However, it takes long time to make them from scratch. One of answers would be Frac-N digital PLL whose most part is digital circuit which is quickly designed with RTL. However, most of them need time-to-digital converters (TDCs) to make phase quantization noise small [1], [2]. The TDC is a key analog block that requires long time to design and calibration which increases complexity. If we have a fractional divider (FDIV) to make a Frac-N PLL by just connecting to an Int-N PLL, it is useful. Some Frac-N PLLs [3], [4] have been published and they have FDIVs. In [3], extra coarse frequency control is needed to generate the frequency information, increasing complexity. In [4], two-step phase interpolation has been proposed to reduce $\Delta \sum$ quantization noise. However, one of phase interpolators (PIs) is put together with the phase detector. It is tough to apply this structure to ordinary PLLs.

The estimation of a reliable velocity–depth model from towed streamer marine seismic data recorded in deep water, especially with a complex seafloor environment, is challenging. The determination of interval velocities from the normal move-out (NMO) of the reflected seismic signals for shallow reflectors (<1 km below the seafloor) is compromised by the combination of a long wave path in the water column and the complex ray paths due to topography, leading to small move-out differences between reflectors. Furthermore, low sediment velocities and deep water produce refraction arrivals only at limited far offsets that contain information about deeper structures. Here, we present an innovative method where towed streamer seismic data are downward continued to the seafloor leading to the collapse of the seafloor reflection and the emergence of refraction events as first arrivals close to zero offset, which are used to determine a high-resolution near surface velocity–depth model using an efficient tomographic method. These velocities are then used to perform pre-stack depth migration. We found that the velocity–depth model derived from tomography of downward continued towed streamer data provides a far superior pre-stack depth migrated image than those produced from velocity–depth models derived from conventional velocity estimation techniques.

Micro Aerial Vehicles (MAVs) have become increasingly popular due to their wide applications in many areas. For autonomous navigation and safe control of MAVs, it is essential to have accurate and reliable velocity and position estimation. However, due to limited computational power and payload, it is still challenging for autonomous operation of MAVs in complex environments. In this paper, we propose a robust and efficient velocity estimation framework for MAVs with a single downward-facing RGB-D camera, which is able to provide metric velocity estimation in three dimensions as well as yaw rate in real-time without the fusion of additional sensors. Unlike traditional algorithms, our method uses kernel cross-correlators (KCCs) to efficiently determine optical flow for motion estimation, which does not rely on costly feature extraction and matching process. Moreover, we utilize depth images to estimate the vertical velocity of MAVs without the assumption of a flat ground. Autonomous flight tests on a quadrotor in complex environments demonstrate the robustness and efficiency of our method.

A low power time-to-digital converter (TDC) with high resolution is presented in this paper. The TDC employs a digital-to-time converter (DTC) to reduce the dynamic range based on a phase-prediction technique. A snapshot circuit is used to reduce the sampling rate from digitally-controlled oscillator (DCO) frequency to reference frequency, thus greatly saving power. In addition, the proposed digital architecture adopts a time-amplifier based TDC (TA-TDC) to achieve high resolution. The proposed TDC is implemented in SMIC 40nm CMOS. Simulation results show that it can achieve a resolution about 0.5ps while totally consuming only 163uW.

Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 μW for all ERSFQ components. The design specifications such as number of junctions and area will be discussed together with the power delivery technique involving an over-pumped feeding Josephson transmission line (JTL).

High-resolution time-to-digital converters (TDCs) with a bidirectional encoder

We present an all-digital phase-locked loop (ADPLL)-based frequency synthesizer for WiMAX applications implemented in 40-nm CMOS. Via frequency planning and design of multiple capacitor-banks in a digitally-controlled oscillator (DCO), the ADPLL covers dual bands of 2.3-2.7 GHz and 3.3-3.8 GHz, while achieving a fine frequency resolution of 25 Hz. The time-to-digital converter (TDC) achieves a resolution of better than 13 ps. Several techniques have been proposed to improve system performance. The whole system is simulated via Verilog-AMS with digital circuits at the gate level. The ADPLL achieves an integrated phase noise of better than -40 dBc from 1 kHz to 10 MHz, and settling time is within 15 us.

A new effective and robust approach to the detection of incompletely resolved peaks, and evaluation of their parameters in high-resolution time-of-flight mass spectra for time-to-digital convertor (TDC) data acquisition mode, is described. The method is based on fast construction of a smoothed continuous curve that approximates the initial data (transformed to a constant relative width of time intervals for ion counting) with respect to precision of measurements. The first derivative of this curve is used for correction of skewness of the peak shape as far as possible. A contribution of the second derivative is subtracted from the smoothed curve for better resolution of partially resolved peaks. The comparison of local maxima of this resulting final curve with those for the initial smoothed curve allows reliable detection of the peaks and to test whether or not they are spoiled by overlapping. Ion counting performed by TDC gives an opportunity to estimate standard deviations of peak locations and their intensities. These values proved to be close to theoretically minimal standard deviations for these parameters for single fully resolved peaks. Thus, estimates of the main parameters of mass peaks by the described method are close to statistically efficient estimators for these parameters.