High-resolution time-to-digital converters (TDCs) with a bidirectional encoder

Radiation detection used in positron emission tomography (PET) exploit the timing information to remove background noise and refine the position measurement through time-of-flight (TOF) information. In PET, very fine time resolution (in the order of 10 ps FWHM) would not only improve contrast in the image, but would also enable real-time image reconstruction without iterative or back-projected algorithms. The current performance limitations will be pushed off through the optimization of faster light emission mechanisms (prompts photons), after which the burden of timing resolution will fall to the readout optoelectronics. Digital SPAD arrays offer compelling possibilities to minimize timing jitter in these future detector systems such per-cell timestamps granularity and per-cell configuration parameters, providing a highly flexible signal processing environment. However, processing hundreds of timestamps per detection event places a toll on the real-time processing, which increases rapidly with embedded channel count. Furthermore, if the processing is sent to an external device such as an FPGA, the bandwidth and related power requirements also increase. The simulation flow presented here offers perspectives on how many time to digital converters (TDC) would be required to reach the 10 ps FWHM CTR range for PET. Using this information, designers can estimate the compromises between timing performance, bandwidth requirements, data transmission, power consumption and real-time dataflow processing in the DAQ at the chip and system level. With a standard 1.1 × 1.1 × 3.0 mm3 LYSO scintillator, the coincidence timing resolution (CTR) changed by less than 3% within the range of 4 to 484 implemented TDCs for evaluated system conditions. On the other hand, an LYSO-based photonic crystal with 2.5% prompt emission rate needs a detector with at least 36 TDCs to reach within 3% CTR of an equivalent array with one TDC per SPAD. This gives significant insights on how this change of crystal material will affect system real time requirements for future detector design.

The principle of tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC) requires finer delay granularity for higher time resolution. Given a tapped delay line constructed with carry chains in an FPGA, it is desirable to find a solution subdividing the intrinsic delay elements further, so that the TDC can achieve a time resolution beyond its cell delay. In this paper, after exploring the available logic resource in Xilinx Kintex UltraScale FPGA, we propose a dual-sampling method to have the TDL status sampled twice. The effect of the new method is equivalent to double the number of taps in the delay line, therefore a significant improvement in time resolution should present. Two TDC channels have been implemented in a Kintex UltraScale FPGA and the effectiveness of the new method is investigated. For fixed time intervals in the range from 0 to 440 ns, the average time resolutions measured by the two TDC channels are respectively 3.9 ps with the dual-sampling method and 5.8 ps by the conventional single-sampling method. In addition, the TDC design maintains advantages of multichannel capability and high measurement throughput in our previous design. Every part of TDC, including dual-sampling, code conversion and on-line calibration could run at 500 MHz clock frequency.

Nuclear physics experiments and medical imaging techniques like Positron Emission Tomography (PET) are moving through time- resolved experiments. Furthermore, the increasing complexity of the phenomena under observation makes mandatory to build a set-up by means of the interconnection of an instrumentation cluster. In this sense, classical Time-to-Digital- Converter (TDC) structure is no more satisfactory, since the number of channels of one measuring unit is no more sufficient. In this contribution, the implementation of a network of TDCs based on Field Programmable-Gate Arrays (FPGAs) is presented. Aim of this contribution is to give the possibility to reach a huge amount of channels, simply by connecting TDCs hosted in different devices without loss in term of precision and resolution. Furthermore, to guarantee fast prototyping and flexibility, all the synchronization algorithm and the TDC are implemented in programmable logic. The idea behind this implementation is a distributed architecture composed of multiple high-resolution TDCs (units of picoseconds) and obtain the timestamps as if they were coming from a single device. The challenge is mainly dictated by the differences in clock frequencies of the devices that compose the network, and can be referred to two problems: the offset leading to different values for the timestamps on different devices, and the gain error, which determines different Least Significant Bits (LSBs) for the measurements. The most relevant problem, the second one, it is addressed by adding an extra channel in each TDC, called sync, which takes care of the synchronization between all the devices which compose the network. In this way, the sync is in charge to measure the clock skew between the TDCs respect to a common signal and consequently normalize all the timestamps.

We present the implementation of a high-resolution Time-to-Digital Converter (TDC) in a Field Programmable Gate Array (FPGA) from Xilinx Virtex-5 family. The design of the TDC is based on a counter and interpolator method. Dedicated carry-in lines in CARRY4 blocks of the Virtex-5 FPGA are utilized for time interpolation, which realizes the fine time measurement within a system clock period. Simulation results show that the delay from CIN to COUT in CARRY4 block is as large as 104 ps. Thus we subdivide the delay cell into finer taps for a higher resolution. Considering the inhomogeneous delay cells, multiple strategies are applied to perform the calibration and to enhance the TDC resolution. Meanwhile, we also apply Place and Route (PAR) constraints to fit our TDC requirements. Finally, a total of 16 TDC channels with a timing performance of about 15 ps RMS are implemented in one FPGA.

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.

A cost-effective field-programmable-gate-array-based pulse processor for biomedical imaging applications

Improving timing resolution in positron emission tomography (PET), thus having fine time information of the detected pulses, is important to increase the reconstructed images signal to noise ratio (SNR) [1]. In the present work, an integrated circuit topology for time extraction of the incoming pulses is evaluated. An accurate simulation including the detector physics and the electronics with different configurations has been developed. The selected architecture is intended for a PET system based on a continuous scintillation crystal attached to a SiPM array. The integrated circuit extracts the time stamp from the first few photons generated when the gamma-ray interacts with the scintillator, thus obtaining the best time resolution. To get the time stamp from the detected pulses, a time to digital converter (TDC) array based architecture has been proposed as in [2] or [3]. The TDC input stage uses a current comparator to transform the analog signal into a digital signal. Individually configurable trigger levels allow us to avoid false triggers due to signal noise. Using a TDC per SiPM configuration results in a very area consuming integrated circuit. One solution to this problem is to join several SiPM outputs to one TDC. This reduces the number of TDCs but, on the other hand, the first photons will be more difficult to be detected. For this reason, it is important to simulate how the time resolution is degraded when the number of TDCs is reduced. Following this criteria, the best configuration will be selected considering the trade-off between achievable time resolution and the cost per chip. A simulation is presented that uses Geant4 for simulation of the physics process and, for the electronic blocks, spice and Matlab. The Geant4 stage simulates the gamma-ray interaction with the scintillator, the photon shower generation and the first stages of the SiPM. The electronics simulation includes an electrical model of the SiPM array and all the integrated circuitry that generates the time stamps. Time resolution results are analyzed using Matlab. The goal is to analyze the best resolution achievable with the SiPM and its degradation due to different circuitry configurations.

This work presents a multi-channel time-to-digital converter (TDC) based on a field-programmable gate array (FPGA). This TDC shares many advantages of custom circuitry but few of the drawbacks. A thorough characterization of the TDC, based on a Xilinx Virtex-6 FPGA, is presented and several performance parameters are described, including distortions due to the FPGA architecture, temperature effects, intra-chip position variation, and chip-to-chip variation. An optimized TDC exhibits 10ps resolution, 3.86LSB integral non-linearity, and a throughput of 300MS/s. Also, measurements are shown for TDC-to-TDC distortion for multi-channel TDCs and simulations are performed to investigate parallelism using multiple TDCs. Results imply that FPGA-based TDCs can achieve high performance, and can be used in a wide range of applications requiring high throughput and accurate time measurements.

A ring-oscillator based multi-mode time-to-digital converter on Xilinx Kintex-7 FPGA

This work proposed a new time-to-digital converter (TDC) utilizing rapid single-flux-quantum circuits. The proposed TDC architecture comprises a counter and a ring oscillator to construct a coarse TDC and a vernier delay line to build a fine TDC, which would maintain the high resolution and high dynamic range of the whole TDC. A TDC with the proposed architecture has been designed, fabricated, and successfully tested. The measurement shows that the designed TDC works correctly with a 5.5 ps resolution, a 1320 ps dynamic range, and a 1.5 LSB differential nonlinearity.

Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning, a self-calibration method is proposed, which allows for the calibration after the tape-out. The method utilizes a ruler DTC(RDTC) as the input signal of TDC to calibrate it. After self-calibration, the resolution of TDC is equal to the RDTC's delay step, so the resolution becomes adjustable by altering the RDTC's delay step. Setting the resolution at 1ps, the integral nonlinearity (INL) is 0.07LSB, the power consumption is 1.37mW at 50MHz with a 1.2V operating voltage and it occupies a core area of 0.018 mm2 in 0.13um CMOS process.

This paper proposes an ultra wide input time interval range, two-step (TS) time-to-digital converter (TDC) with a foreground coarse gain calibration. The proposed TS TDC converts the input time intervals by sequentially using two TDCs that have different dynamic ranges and time resolutions. The fine 2nd stage incorporates a pulse-shrinking ring architecture to achieve sub-gate-delay resolution, whereas the coarse 1st stage uses a simple ring-oscillator-based TDC. The time resolution of the 1st stage is foreground-calibrated at start-up by utilizing the fine 2nd stage TDC. The TDC simulated in a 0.18 pm standard CMOS technology demonstrates 1.8 ps resolution and 16 bit range that corresponds to 118 ns input time interval with 0.07 mm2 area. It operates at 3.3 MS/s with 12.7 mW, and achieves 1.28 ps single-shot precision.

In this paper, a novel in-pixel time-to-digital converter (TDC) for 3D time-of-flight cameras is presented. Coarse---fine architecture has been used to guarantee both wide dynamic range and high time resolution. The proposed TDC exploits pulse-train time amplifier (TA) to further improve the time resolution and optimize time error performance. The 11-bit TDC provides 62.5 ps resolution and 126 ns full-scale range. Simulation results indicate the TDC achieves a DNL of under 0.52 LSB and INL less than 0.8 LSB. Both the TA and TDC are designed in GSMC CIS 0.18 μm 1P6M technology.

A new Vernier-type time-to-digital converter (TDC) with low resource consumption and medium performance is designed and evaluated in a Xilinx Kintex-7 field programmable gate array (FPGA). The converter requires only one ring oscillator, and its resolution is the period difference between two signals of the oscillation pulse and system clock. The conversion is finished by judging the alignment between the oscillation pulse with either the rising edge or the falling edge of the system clock. The difficulty of this new method is the design of the ring oscillator, which is required to oscillate with a frequency closing to the system clock frequency in any position of FPGA to keep TDC performance less position-dependent. The design of such a ring oscillator is proposed and 28 identical TDCs are implemented in 14 clock regions of the FPGA for performance evaluation. Through the TDC bin width measurement, the average resolution of 28 TDCs is 61.1 ps and the variation of resolution over location is 31.5 ps. Through time-interval measurement, the average time-interval RMS precision in 14 clock regions is 28.9 ps and the corresponding precision variation over location is 8.7 ps. The test results show that the proposed TDC is applicable, in particular to cases that multi-channel capability with medium performance is highly required.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array