A ring-oscillator based multi-mode time-to-digital converter on Xilinx Kintex-7 FPGA

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

The full hardware solution introduced in our previous work could implement multi-channel time-to-digital converters (TDCs) in a Xilinx Kintex-7 FPGA with better than 10 ps RMS precision and 710 MHz measurement throughput. Based on these fundamental TDC blocks, we propose a method to improve the time precision further by merging multiple TDC blocks, which is equivalent to increasing the number of TDC bins multiple times. Two merged TDC channels, each with four TDC blocks, are implemented in the Kintex-7 FPGA and the performance is evaluated. For fixed time intervals in the range from 0 to 20 ns, the average RMS precision measured by the two TDC channels reaches 3.1 ps. The test results show that the FPGA based multi-channel TDC system can be flexibly configured as either more TDC channels with a low time precision or fewer TDC channels with a high time precision.

The principle of tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC) requires finer delay granularity for higher time resolution. Given a tapped delay line constructed with carry chains in an FPGA, it is desirable to find a solution subdividing the intrinsic delay elements further, so that the TDC can achieve a time resolution beyond its cell delay. In this paper, after exploring the available logic resource in Xilinx Kintex UltraScale FPGA, we propose a dual-sampling method to have the TDL status sampled twice. The effect of the new method is equivalent to double the number of taps in the delay line, therefore a significant improvement in time resolution should present. Two TDC channels have been implemented in a Kintex UltraScale FPGA and the effectiveness of the new method is investigated. For fixed time intervals in the range from 0 to 440 ns, the average time resolutions measured by the two TDC channels are respectively 3.9 ps with the dual-sampling method and 5.8 ps by the conventional single-sampling method. In addition, the TDC design maintains advantages of multichannel capability and high measurement throughput in our previous design. Every part of TDC, including dual-sampling, code conversion and on-line calibration could run at 500 MHz clock frequency.

A new Vernier-type time-to-digital converter (TDC) with low resource consumption and medium performance is designed and evaluated in a Xilinx Kintex-7 field programmable gate array (FPGA). The converter requires only one ring oscillator, and its resolution is the period difference between two signals of the oscillation pulse and system clock. The conversion is finished by judging the alignment between the oscillation pulse with either the rising edge or the falling edge of the system clock. The difficulty of this new method is the design of the ring oscillator, which is required to oscillate with a frequency closing to the system clock frequency in any position of FPGA to keep TDC performance less position-dependent. The design of such a ring oscillator is proposed and 28 identical TDCs are implemented in 14 clock regions of the FPGA for performance evaluation. Through the TDC bin width measurement, the average resolution of 28 TDCs is 61.1 ps and the variation of resolution over location is 31.5 ps. Through time-interval measurement, the average time-interval RMS precision in 14 clock regions is 28.9 ps and the corresponding precision variation over location is 8.7 ps. The test results show that the proposed TDC is applicable, in particular to cases that multi-channel capability with medium performance is highly required.

This paper presents the design of a CMOS time-to-digital converter (TDC) used in a direct time-of-flight laser radar line receiver consisting of an array of single-photon avalanche diodes (SPADs) and 256 TDCs. The TDCs use the Nutt interpolation method, where the start/stop fine interpolators are based on a cyclic converter architecture. The cyclic converters use a delay-line-based time interval amplifier to double the quantization residue after each quantization cycle. The time amplifier, and the entire TDC array, does not need any biasing nor does the TDC results need any post-processing to provide sub-100-ps precision and uniformity across the TDC array, therefore making the design very robust and appealing for large designs where hundreds of TDCs are needed on a single chip. Fabricated in a 0.35μm CMOS technology, a single TDC channel occupies an area of 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes a power of 1.17 mW @ 100 kHz measurement rate. The TDC has a measurement range of 640 ns, and with a resolution of 15 bits, the LSB is 20 ps. Linearity is ensured by the Nutt interpolation method while the rms single-shot precision of the TDC channel is 72 ps. Thus, when LIDAR applications are considered, the TDC is capable of providing a range of 96 m with a precision of 1 cm without any post-processing or calibration.

We present the implementation of a high-resolution Time-to-Digital Converter (TDC) in a Field Programmable Gate Array (FPGA) from Xilinx Virtex-5 family. The design of the TDC is based on a counter and interpolator method. Dedicated carry-in lines in CARRY4 blocks of the Virtex-5 FPGA are utilized for time interpolation, which realizes the fine time measurement within a system clock period. Simulation results show that the delay from CIN to COUT in CARRY4 block is as large as 104 ps. Thus we subdivide the delay cell into finer taps for a higher resolution. Considering the inhomogeneous delay cells, multiple strategies are applied to perform the calibration and to enhance the TDC resolution. Meanwhile, we also apply Place and Route (PAR) constraints to fit our TDC requirements. Finally, a total of 16 TDC channels with a timing performance of about 15 ps RMS are implemented in one FPGA.

A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems

This paper presents a temperature compensation design for carry chain based Time-to-Digital Converter (TDC) in FPGA. The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain which shows all TDC channels have the similar temperature-LUT coefficient. Accordingly, a simplified temperature compensation scheme by using a dedicated correction channel to measure the coefficient and correct fine time result for all TDC channels is implemented and tested. This method shows only few picosecond errors for both simulation and measurement. With this compensation approach, a 21ps RMS TDC resolution has been achieved in Cyclone II FPGA under a wide temperature range from 10°C to 75°C. Several design key points are also described in this paper.

The readout electronics in time-of-flight positron emission tomography (TOF-PET) detector modules conventionally contain a separate timing circuit and a separate energy measurement circuit. For channel-by-channel readouts, the front-end electronics will be unacceptably large and must rely on application specific integrated circuit (ASIC) chips. In this paper, we present a novel field programmable gate array (FPGA)-based readout scheme that unifies the time and energy measurements with only one analog amplifier per channel in addition to the FPGA. By constructing a simple and effective fast linear discharge circuit, one time-to-digital converter (TDC) per channel can implement time and energy readouts simultaneously with a short measurement dead time. To evaluate the performance of the new approach, a 16-channel PET detector module consisting of LYSO crystals coupled with a silicon photomultiplier (SiPM) array was constructed connecting to the readout electronics. Using a reference detector with a 164.7-ps time resolution to perform 22Na coincidence measurements, the average energy, and time resolution among 16 channels were measured as 12.44% and 372.6 ps, respectively. The typical measurement dead time is approximately 300 ns. The test results show the simplicity and feasibility of the proposed readout scheme, which is particularly useful for laboratory instrumentation.

In this paper, a time-to-digital converter (TDC) based on 4 multi-phase clocks is implemented in a XILINX's Virtex4 FPGA. Profit from the PLL technology we can adjust the clock phase precisely. In this case, 4 multi-phase clocks have the 0°, 90°, 180°, 270° phase shift are generated. Each clock's rising edge has the same delay to the previous clock. Based on those 4 multi-phase clocks, we can divide one clock period into 4 same parts. The bin size of the TDC can be proved to 1/4 clock period. It is a new approach to come true the time interpolation within one clock period. The TDC based on multi-phase clock needs less logic resource than other kind TDC. Its high precision, high integrated level and large dynamic range can fit the demands very well. The performance of the multi-phase clock based TDC was tested. The bin size (resolution) of each channel is 0.757ns and the RMS (precision) is less than 0.5ns. The dynamic range is longer than 1 second. 64 TDC channels are realized in only one FPGA on a 15cm * 15cm board.

This work presents a multi-channel time-to-digital converter (TDC) based on a field-programmable gate array (FPGA). This TDC shares many advantages of custom circuitry but few of the drawbacks. A thorough characterization of the TDC, based on a Xilinx Virtex-6 FPGA, is presented and several performance parameters are described, including distortions due to the FPGA architecture, temperature effects, intra-chip position variation, and chip-to-chip variation. An optimized TDC exhibits 10ps resolution, 3.86LSB integral non-linearity, and a throughput of 300MS/s. Also, measurements are shown for TDC-to-TDC distortion for multi-channel TDCs and simulations are performed to investigate parallelism using multiple TDCs. Results imply that FPGA-based TDCs can achieve high performance, and can be used in a wide range of applications requiring high throughput and accurate time measurements.

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.

The wave union (WU) method can improve the performance of time-to-digital converters (TDCs) without consuming additional logic resources, and has therefore been widely adopted in field-programmable gate array (FPGA)-TDC designs. However, the propagation requirement of the WU pulse train forces the tapped delay line (TDL) to span longer than one clock period, such that conventional encoders must introduce extra dead time to ensure correct decoding. This article presents a low-deadtime, high-precision FPGA-based TDC that combines a 4edge WU-A scheme, dual sampling, and a resource-efficient event-aggregation encoder. With the proposed eventaggregation encoding, the WU edge positions associated with different events on the TDL are aggregated and encoded with negligible additional FPGA logic-resource usage, reducing the dead time of WU-based FPGA-TDCs to one clock cycle. In addition, to address the more severe bubble errors in advanced FPGA technology nodes, we apply clock-skew-aware placement constraints to optimize the TDL clock distribution. For the first time, a 4-edge WU-A TDC is implemented within a single clock region on a 16nm UltraScale+ FPGA. The optimized design achieves an equivalent bin width of 0.9 ps and an equivalent quantization error of 0.26 ps, improving the measured timing precision to 1.45-2.19 ps.

An FPGA-based 500 M samples per second throughput time-to-digital converter without ineffective bin

Nuclear physics experiments and medical imaging techniques like Positron Emission Tomography (PET) are moving through time- resolved experiments. Furthermore, the increasing complexity of the phenomena under observation makes mandatory to build a set-up by means of the interconnection of an instrumentation cluster. In this sense, classical Time-to-Digital- Converter (TDC) structure is no more satisfactory, since the number of channels of one measuring unit is no more sufficient. In this contribution, the implementation of a network of TDCs based on Field Programmable-Gate Arrays (FPGAs) is presented. Aim of this contribution is to give the possibility to reach a huge amount of channels, simply by connecting TDCs hosted in different devices without loss in term of precision and resolution. Furthermore, to guarantee fast prototyping and flexibility, all the synchronization algorithm and the TDC are implemented in programmable logic. The idea behind this implementation is a distributed architecture composed of multiple high-resolution TDCs (units of picoseconds) and obtain the timestamps as if they were coming from a single device. The challenge is mainly dictated by the differences in clock frequencies of the devices that compose the network, and can be referred to two problems: the offset leading to different values for the timestamps on different devices, and the gain error, which determines different Least Significant Bits (LSBs) for the measurements. The most relevant problem, the second one, it is addressed by adding an extra channel in each TDC, called sync, which takes care of the synchronization between all the devices which compose the network. In this way, the sync is in charge to measure the clock skew between the TDCs respect to a common signal and consequently normalize all the timestamps.