A high-resolution time-to-digital converter based on multi-phase clock implement in field-programmable-gate-array

We propose a single-slop ADC with a time to digital converter (TDC) that uses a multi-phase clock. Single-slope ADCs have been used as column parallel ADCs for CMOS image sensors. When the TDC with resolution of n bits is adapted to the ADC, the conversion time is reduced by a factor of 2n. Applying the TDC that uses multi-phase-clock signal reduced the number of circuit elements, achieved consistency between the single-slope ADC and the TDC, and realized robust meta-stability. We designed a 12-bit ADC, which consists of the 3-bit TDC and the 9-bit-single-slope ADC, by using a 0.25-µm CMOS process. Through SPICE simulation, we confirmed our single-slop ADC to be more consistent, have more robust meta-stability, and achieve higher-speed ADC operation at 200-MHz clock than the conventional single-slope ADC. The simulated DNL and INL were ±0.25 LSB and ±0.43 LSB.

The full hardware solution introduced in our previous work could implement multi-channel time-to-digital converters (TDCs) in a Xilinx Kintex-7 FPGA with better than 10 ps RMS precision and 710 MHz measurement throughput. Based on these fundamental TDC blocks, we propose a method to improve the time precision further by merging multiple TDC blocks, which is equivalent to increasing the number of TDC bins multiple times. Two merged TDC channels, each with four TDC blocks, are implemented in the Kintex-7 FPGA and the performance is evaluated. For fixed time intervals in the range from 0 to 20 ns, the average RMS precision measured by the two TDC channels reaches 3.1 ps. The test results show that the FPGA based multi-channel TDC system can be flexibly configured as either more TDC channels with a low time precision or fewer TDC channels with a high time precision.

The wave union (WU) method can improve the performance of time-to-digital converters (TDCs) without consuming additional logic resources, and has therefore been widely adopted in field-programmable gate array (FPGA)-TDC designs. However, the propagation requirement of the WU pulse train forces the tapped delay line (TDL) to span longer than one clock period, such that conventional encoders must introduce extra dead time to ensure correct decoding. This article presents a low-deadtime, high-precision FPGA-based TDC that combines a 4edge WU-A scheme, dual sampling, and a resource-efficient event-aggregation encoder. With the proposed eventaggregation encoding, the WU edge positions associated with different events on the TDL are aggregated and encoded with negligible additional FPGA logic-resource usage, reducing the dead time of WU-based FPGA-TDCs to one clock cycle. In addition, to address the more severe bubble errors in advanced FPGA technology nodes, we apply clock-skew-aware placement constraints to optimize the TDL clock distribution. For the first time, a 4-edge WU-A TDC is implemented within a single clock region on a 16nm UltraScale+ FPGA. The optimized design achieves an equivalent bin width of 0.9 ps and an equivalent quantization error of 0.26 ps, improving the measured timing precision to 1.45-2.19 ps.

The principle of tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC) requires finer delay granularity for higher time resolution. Given a tapped delay line constructed with carry chains in an FPGA, it is desirable to find a solution subdividing the intrinsic delay elements further, so that the TDC can achieve a time resolution beyond its cell delay. In this paper, after exploring the available logic resource in Xilinx Kintex UltraScale FPGA, we propose a dual-sampling method to have the TDL status sampled twice. The effect of the new method is equivalent to double the number of taps in the delay line, therefore a significant improvement in time resolution should present. Two TDC channels have been implemented in a Kintex UltraScale FPGA and the effectiveness of the new method is investigated. For fixed time intervals in the range from 0 to 440 ns, the average time resolutions measured by the two TDC channels are respectively 3.9 ps with the dual-sampling method and 5.8 ps by the conventional single-sampling method. In addition, the TDC design maintains advantages of multichannel capability and high measurement throughput in our previous design. Every part of TDC, including dual-sampling, code conversion and on-line calibration could run at 500 MHz clock frequency.

A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems

In this paper, we propose a high precision vernier type delta-sigma time to digital converter (TDC) architecture. The time resolution of conventional delta-sigma TDC that has a delay stage consists of a delay element and three multiplexers is strongly dependent on the delay time for a delay element used in the delay stage and the measurement time. However, the delay time is limited by the complementary metal oxide semiconductor (CMOS) process and thus, the longer measurement time result in the longer operation time. To solve these problems, we introduce a new delay stage consisting of two delay elements and four multiplexers to the conventional delta-sigma TDC. Proposed delta-sigma TDC can relatively shorten the delay time and improve the time resolution compared with the conventional delta-sigma TDC. The effectiveness of the proposed method is confirmed by simulations using MATLAB/Simulink. When the delay time is reduced to one quarter as compared with the conventional delta-sigma TDC, the signal to noise ratio (SNR) of the proposed delta-sigma TDC is improved by 12.9dB.

This article presents a low-power highly linear multichannel data acquisition (DAQ) system for silicon photomultiplier (SiPM) readout. A low-input impedance current-mode front-end with a programmable current gain is developed to achieve high-precision charge readout over a large dynamic range. An integrated 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) shared by 16 readout channels in a time-multiplexed manner is designed to reduce the overall chip area and power consumption of the SiPM readout. Implementation challenges of field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) including bubble error, zero length bins, interclock region nonlinearity, and chain overflow, are addressed for high accuracy timing measurement. Multichain averaging is developed to improve the TDC linearity. Fabricated in a 180-nm CMOS process, the current-mode 16-channel readout application-specific integrated circuit (ASIC) achieves 3.6% maximum gain nonlinearity over an input dynamic range of 800 pC with dissipating 3.89 mW of power per readout channel, and the ADC achieves an SFDR of 58.34 dB and an SNDR of 51.37 dB at 16 MS/s. Implemented in a Xilinx 28-nm Kintex-7 FPGA, the 32-channel TDC achieves a 15-ps root mean square (RMS) resolution, a differential nonlinearity (DNL) of less than 4 ps, and an integral nonlinearity (INL) of less than 10 ps.

A new approach for pipeline time-to-digital converters (TDCs) is introduced in this paper. The analog interpolation and voltage amplification methods for digitalizing the time intervals between the rising edges of two input signals are employed in the recommended converter. It consists of four 2.5b/stage time-to-digital converters and three voltage amplifiers (VAs) and will be a 9-bit pipeline TDC. Besides, a new VA is suggested in this paper. The delay cells such as delay line TDCs and vernier delay line TDCs (VDL–TDCs) are not used in this converter. Moreover, a triple-slope conversion is achieved by performing of the interpolation. Lots of advantages can be mentioned for the proposed converter such as; lower complexity, lower temperature sensitivity, power supply and process (PVT) variations, and higher accuracy in comparison with the time-to-digital converters which have been proposed previously. Furthermore, the differential non linearity (DNL) and the integral non linearity (INL) errors are decreased while the dynamic range, the time resolution, and the linear range of the TDC are developed significantly. The simulation results for INL and DNL in the proposed TDC are 0.83 LSB and 0.92 LSB, correspondingly. In addition, the time resolution is improved to 0.234 ps. To verify the validity of theoretical analysis, designing and simulation of the TDC is done in TSMC 45 nm CMOS technology. The comparison between the theoretical analysis and simulation results approves the superiorities and characteristics of the proposed TDC.

A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

This work proposed a new time-to-digital converter (TDC) utilizing rapid single-flux-quantum circuits. The proposed TDC architecture comprises a counter and a ring oscillator to construct a coarse TDC and a vernier delay line to build a fine TDC, which would maintain the high resolution and high dynamic range of the whole TDC. A TDC with the proposed architecture has been designed, fabricated, and successfully tested. The measurement shows that the designed TDC works correctly with a 5.5 ps resolution, a 1320 ps dynamic range, and a 1.5 LSB differential nonlinearity.

A ring-oscillator based multi-mode time-to-digital converter on Xilinx Kintex-7 FPGA

Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 μW for all ERSFQ components. The design specifications such as number of junctions and area will be discussed together with the power delivery technique involving an over-pumped feeding Josephson transmission line (JTL).

This paper demonstrates a low-cost wide dynamic range FPGA time-to-digital converter (TDC) and a time-to-amplitude converter (TAC) based on an embedded XOR gate of the FPGA and a low-complexity circuitry. TACs and TDCs are important for distance measurements in LiDAR systems in a wide range of applications from self-driving cars to topographic mapping. LiDAR&#x2019;s high cost, relatively large size and complexity are important implementation challenges that need to be addressed. In the literature, external circuits are used to provide low phase noise clock signals into the FPGA TDC to measure long range time intervals adding to the complexity and cost. Our TDC can measure a wide dynamic range of 1 ms with high precision using a low-cost FPGA board. Calibration using dynamic phase-shifting (DPS) is conducted with a resolution of 18 ps. The performance measurements gave us insight on the relative temperature insensitive regions for operating the TDC. The ideal range was found to be 24&#x00B0;C to 39&#x00B0;C. We also present a novel TAC design to demonstrate that one XOR gate of a low-cost Artix-7 FPGA and a simple low-cost circuitry can detect a phase difference as low as 18 ps. The TAC&#x2019;s linearity is presented through INL and DNL test results. For every additional channel, our TAC requires only one XOR gate in the FPGA chip and a low complexity circuitry. This allows for multichannel operation and larger area availability for use in other implementations. Performance measurements show our TAC to be highly insensitive to temperature and voltage changes.

We present the implementation of a high-resolution Time-to-Digital Converter (TDC) in a Field Programmable Gate Array (FPGA) from Xilinx Virtex-5 family. The design of the TDC is based on a counter and interpolator method. Dedicated carry-in lines in CARRY4 blocks of the Virtex-5 FPGA are utilized for time interpolation, which realizes the fine time measurement within a system clock period. Simulation results show that the delay from CIN to COUT in CARRY4 block is as large as 104 ps. Thus we subdivide the delay cell into finer taps for a higher resolution. Considering the inhomogeneous delay cells, multiple strategies are applied to perform the calibration and to enhance the TDC resolution. Meanwhile, we also apply Place and Route (PAR) constraints to fit our TDC requirements. Finally, a total of 16 TDC channels with a timing performance of about 15 ps RMS are implemented in one FPGA.

A new Vernier-type time-to-digital converter (TDC) with low resource consumption and medium performance is designed and evaluated in a Xilinx Kintex-7 field programmable gate array (FPGA). The converter requires only one ring oscillator, and its resolution is the period difference between two signals of the oscillation pulse and system clock. The conversion is finished by judging the alignment between the oscillation pulse with either the rising edge or the falling edge of the system clock. The difficulty of this new method is the design of the ring oscillator, which is required to oscillate with a frequency closing to the system clock frequency in any position of FPGA to keep TDC performance less position-dependent. The design of such a ring oscillator is proposed and 28 identical TDCs are implemented in 14 clock regions of the FPGA for performance evaluation. Through the TDC bin width measurement, the average resolution of 28 TDCs is 61.1 ps and the variation of resolution over location is 31.5 ps. Through time-interval measurement, the average time-interval RMS precision in 14 clock regions is 28.9 ps and the corresponding precision variation over location is 8.7 ps. The test results show that the proposed TDC is applicable, in particular to cases that multi-channel capability with medium performance is highly required.