Column parallel single-slope ADC with time to digital converter for CMOS imager

In this paper, a time-to-digital converter (TDC) based on 4 multi-phase clocks is implemented in a XILINX's Virtex4 FPGA. Profit from the PLL technology we can adjust the clock phase precisely. In this case, 4 multi-phase clocks have the 0°, 90°, 180°, 270° phase shift are generated. Each clock's rising edge has the same delay to the previous clock. Based on those 4 multi-phase clocks, we can divide one clock period into 4 same parts. The bin size of the TDC can be proved to 1/4 clock period. It is a new approach to come true the time interpolation within one clock period. The TDC based on multi-phase clock needs less logic resource than other kind TDC. Its high precision, high integrated level and large dynamic range can fit the demands very well. The performance of the multi-phase clock based TDC was tested. The bin size (resolution) of each channel is 0.757ns and the RMS (precision) is less than 0.5ns. The dynamic range is longer than 1 second. 64 TDC channels are realized in only one FPGA on a 15cm * 15cm board.

A time-to-digital converter (TDC) is proposed to replace the multi-bit quantizer and the multi-bit feedback DAC of traditional voltage-mode ΣΔ modulator. Since time-mode systems process analog signals encoded in the time dimension rather than the voltage dimension, the proposed time-mode TDC makes the multi-bit ΣΔ ADC digital friendly and more suitable for nanometric technologies. A pulse-width-modulator (PWM) converts the sampled-and-held voltage-sample to a digital pulse whose width is proportional to the voltage level of the sample. Then, the TDC generates a digital code that corresponds to the pulse width. Simultaneously, the TDC provides a time-quantized feedback pulse for the ΣΔ modulator, emulating the voltage-DAC in a conventional ΣΔ ADC. Linearity, jitter and data-dependent-delay effects on the performance of the proposed architecture are analyzed. A chip prototype is fabricated in TI 65 nm digital CMOS process. THD of 67 dB is achieved which corresponds to a TDC's DNL of less than 0.8 ps without calibration. Measurements show that the ΣΔ-modulator achieves a dynamic range of 68 dB and the TDC consumes 5.66 mW at 250 MHz event rate while occupying 0.006 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper presents a cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs), targeted for a synthesizable all-digital phase locked loop (ADPLL). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (P&R) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of P&R mismatch is characterized in calibration mode, and utilized to achieve a minimum TDC resolution of 5.5 ps. The TDC was fabricated in a 65 nm CMOS process, and occupies 0.006 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

&lt;p&gt;The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.&lt;/p&gt;

&lt;p&gt;The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.&lt;/p&gt;

This paper presents a CMOS realization of a time-to-digital converter (TDC) for nuclear physics experiments. An innovative and robust architecture, already used in a previous TDC version with 1 ns of bin size, has been adopted and improved with the aim to achieve a 500-ps bin size. The TDC has eight input channels plus a common channel. It can store up to 32 events per channel with a double-hit resolution of 8 ns. It can realize common-start and common-stop operations. It has 4.2 ms of input range with a 125-MHz system clock. The chip uses an asynchronous interpolator system based on a delay-locked line to increase the coarse resolution. It has been fabricated in a double-metal single poly n-well, 1-/spl mu/m CMOS process with an area of about 77 mm/sup 2/. Measurements show that the TDC has better performance compared to similar devices, especially the time resolution below 250 ps.

Based on the parallel DTCs as delay cells, a 4-bit TDC with adjustable 0.7ps∼1.4ps resolution and 11ps∼22ps dynamic range is proposed in this paper. In this design, an extremely high resolution DTC is presented, achieving 15.6fs delay per LSB. By utilizing 16 DTCs which are adjusted to have the same time interval among two neighboring DTCs, a highly linear TDC is realized. To avoid the manual tuning, a self-calibration method is proposed, which allows for the calibration after the tape-out. The method utilizes a ruler DTC(RDTC) as the input signal of TDC to calibrate it. After self-calibration, the resolution of TDC is equal to the RDTC's delay step, so the resolution becomes adjustable by altering the RDTC's delay step. Setting the resolution at 1ps, the integral nonlinearity (INL) is 0.07LSB, the power consumption is 1.37mW at 50MHz with a 1.2V operating voltage and it occupies a core area of 0.018 mm2 in 0.13um CMOS process.

An all-digital phase-locked loop (ADPLL) with all components working with time interval or period signals is demonstrated. The ADPLL consists mainly of a free-running ring oscillator (FRO), a time to digital converter (TDC), a digitally controlled oscillator (DCO), a digital divider and a digital loop filter. In the proposed architecture, the TDC and DCO have an equal time resolution from the common FRO. The digital divider keeps the loop gain constant when the frequency multiplication factor changes. As a result, the ADPLL is inherently stable regardless of the variations of the process, supply voltage and temperature (PVT). The ADPLL is fabricated in 0.13 ¿m CMOS process. Measurement results show that it works well over wide operation conditions, with the input frequencies ranging from 37.5 KHz to 25 MHz, frequency multiplication factors from 10 to 255, output frequencies from 10 MHz to 500 MHz, and supply voltages from 0.6 V to 1.6 V.

Herein, we present a recirculating (RC) cyclic Vernier time-to-digital converter (TDC) using dynamic element matching and a register-based time amplifier (TA). The RC TDC reuses a single conversion stage for multiple conversions that are suitable for low power and compact realization. Good matching is achieved between multiple conversions because the same stage is reused. Processing the amplified residue further enhances the TDC resolution. We propose a new TA based on a time register that achieves a well-controlled time magnification over a wide input range. Unlike conventional approaches based on regeneration or meta-stability, the register-based TA does not suffer from a narrow input range. The proposed TA achieves a relatively high gain accuracy (< 1.5%) over a wide input range from 40 to 400 ps. Compact TDC implementation is further facilitated using the multiphase operation of a gated ring oscillator (GRO) in a cyclic Vernier structure. Using the phase-preserving characteristic of the GRO, the mismatch is first order shaped by data weight averaging. The RC TDC fabricated using a 28-nm CMOS process is realized in a small area of 0.0096 mm2. Measurements show that the TDC can be successfully configured into four gain modes with a resolution of 11.5, 7.7, 5.8, and 4.7 ps in a 12-bit dynamic range. The full range linearity measurement shows an integral nonlinearity of less than 1.48 LSB. The power consumption is 0.188 mW at a conversion rate of 3.51 MHz, leading to a favorable figure of merit of 0.032 pJ/conv.-step. The results show the effectiveness of the RC structure in realizing a high-performance, compact TDC.

In this paper, we propose a digital-to-time converter (DTC) design for Fractional-N Sub-sampling Phase-Locked Loop (SSPLL). The proposed design employs a parallel switching structure, re-timing technique, and complementary circuit to improve the linearity of the DTC. Designed in 65 nm CMOS process, this DTC design operates at 100 MHz with a 180 fs resolution and a delay range of $\mathbf{1 8 4 ~ p s}$. For nonlinear performance, integral nonlinearity (INL) is within 216 fs, while Differential Nonlinearity (DNL) remains within 9 fs. It remains competitive compared to state-of-art DTC design. Behavioral-level simulations are conducted for the SSPLL, and a gain calibration module is integrated into the system to calibrate the DTC gain.

This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of $\sqrt {2N} $ improvement in TDC resolution with $N$ parallel TDC channels. Suppressed noise in the TDC allows the ADPLL to achieve superior jitter performance in both theoretical calculations and simulation results. In order to allow fast portability between process nodes, short design cycle time, ease of modification, and flexibility, ADPLL architecture is designed completely in register transfer level intensive Verilog code and the implementation is synthesized in order to obtain final microelectronic design schematics. In comparison to similar work in the literature, postlayout simulation results show that the designed ADPLL achieves period jitter of 1.78 ps$_{rms}$ with a layout area of 0.09 mm$^{2}$ in 65 nm CMOS process and power consumption of 17.5 mW at 800 MHz.

A 5-ps Vernier sub-ranging time-to-digital converter with DNL calibration

A simple time-to-digital converter (TDC), capable of detecting not only phase difference but also frequency difference, is presented. The proposed TDC guarantees pull-in even for PLLs with the lowest loop gain. The TDC is fabricated in a 65 nm CMOS process and dissipates 0.37 mW from a 1.2 V supply at 25 MHz clock frequency.

A fractional-N digital phase-locked loop (DPLL) with ring oscillator based injection-locked frequency divider (ILFD) and parallel sampling phase samplers is presented. The ILFD utilizes dual path injection technique to achieve wide locking range (4.2–23 GHz) and low power consumption. A low-power parallel sampling phase sampler based time-to-digital converter (TDC), which achieves sub-gate-delay resolution by sampling the ILFD’s multi-phase outputs using parallel sampling technique, is proposed. The TDC resolution is determined by delay spacing between successive sampling clocks, which is ensured through digital calibration loops. Due to injection locking, no calibration is required to normalize the TDC step to the DCO output period. A hybrid high speed counter architecture, combining a 2 bit asynchronous counter and a 6 bit synchronous counter, is proposed to achieve high speed (>4 GHz) operation with low power consumption. The proposed design is fabricated in a 65 nm CMOS process and occupies 0.1 mm2. The synthesizer covers 13.6–16.8 GHz output and dissipates 8.5 mW. The measured output phase noise achieves −89 dBc/Hz and −125 dBc/Hz at 100 kHz and 10 MHz offsets, respectively. The measured jitter is less than 0.43 ps.

This paper presents design techniques of a multiphase clock generator using a low-jitter delay-locked loop (DLL) or its array for the developments of high-resolution multi-channel time-to-digital converters (TDCs). The low-jitter technologies for both a single DLL and an array of DLL are discussed. Based on the previous work on the design of a single DLL with 32 delay cells, an array of mixed-mode low-jitter DLLs is proposed for achieving smaller time taps. The array of DLL is successfully designed and embedded into a prototype chip of a three-channel high-resolution TDC in 0.35 CMOS process. The operational range of the DLL in the array is from 50 MHz to 120 MHz. The RMS value of measured cycle-to-cycle jitter in the DLL is about 7 ps while the peak-to-peak value is about 20 ps. A bin size of 71 ps can be achieved by using a reference clock of 100 MHz. The DNL and INL of the evaluated chip are 0.58 LSB and 0.63 LSB, respectively. The static power dissipation of the DLL array is about 23 mW.