An FPGA-based 500 M samples per second throughput time-to-digital converter without ineffective bin

The principle of tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC) requires finer delay granularity for higher time resolution. Given a tapped delay line constructed with carry chains in an FPGA, it is desirable to find a solution subdividing the intrinsic delay elements further, so that the TDC can achieve a time resolution beyond its cell delay. In this paper, after exploring the available logic resource in Xilinx Kintex UltraScale FPGA, we propose a dual-sampling method to have the TDL status sampled twice. The effect of the new method is equivalent to double the number of taps in the delay line, therefore a significant improvement in time resolution should present. Two TDC channels have been implemented in a Kintex UltraScale FPGA and the effectiveness of the new method is investigated. For fixed time intervals in the range from 0 to 440 ns, the average time resolutions measured by the two TDC channels are respectively 3.9 ps with the dual-sampling method and 5.8 ps by the conventional single-sampling method. In addition, the TDC design maintains advantages of multichannel capability and high measurement throughput in our previous design. Every part of TDC, including dual-sampling, code conversion and on-line calibration could run at 500 MHz clock frequency.

This work presents a multi-channel time-to-digital converter (TDC) based on a field-programmable gate array (FPGA). This TDC shares many advantages of custom circuitry but few of the drawbacks. A thorough characterization of the TDC, based on a Xilinx Virtex-6 FPGA, is presented and several performance parameters are described, including distortions due to the FPGA architecture, temperature effects, intra-chip position variation, and chip-to-chip variation. An optimized TDC exhibits 10ps resolution, 3.86LSB integral non-linearity, and a throughput of 300MS/s. Also, measurements are shown for TDC-to-TDC distortion for multi-channel TDCs and simulations are performed to investigate parallelism using multiple TDCs. Results imply that FPGA-based TDCs can achieve high performance, and can be used in a wide range of applications requiring high throughput and accurate time measurements.

The wave union (WU) method can improve the performance of time-to-digital converters (TDCs) without consuming additional logic resources, and has therefore been widely adopted in field-programmable gate array (FPGA)-TDC designs. However, the propagation requirement of the WU pulse train forces the tapped delay line (TDL) to span longer than one clock period, such that conventional encoders must introduce extra dead time to ensure correct decoding. This article presents a low-deadtime, high-precision FPGA-based TDC that combines a 4edge WU-A scheme, dual sampling, and a resource-efficient event-aggregation encoder. With the proposed eventaggregation encoding, the WU edge positions associated with different events on the TDL are aggregated and encoded with negligible additional FPGA logic-resource usage, reducing the dead time of WU-based FPGA-TDCs to one clock cycle. In addition, to address the more severe bubble errors in advanced FPGA technology nodes, we apply clock-skew-aware placement constraints to optimize the TDL clock distribution. For the first time, a 4-edge WU-A TDC is implemented within a single clock region on a 16nm UltraScale+ FPGA. The optimized design achieves an equivalent bin width of 0.9 ps and an equivalent quantization error of 0.26 ps, improving the measured timing precision to 1.45-2.19 ps.

This paper proposes multi-path delay line (MPDL) time-to-digital converter (TDC). Instead of traditional tapped delay line (TDL) TDC, the proposed MPDL-TDC can improve the linearity performance effectively. Implemented in a Xilinx XC5VLX110T-1FF1136 field-programmable gate array (FPGA) device, the proposed MPDL-TDC has 60 ps time resolution, and the ranges of differential non-linearity (DNL) and integral non-linearity (INL) are [−0.52,0.52] and [−0.79,1.06] least-significant-bit (LSB), respectively. Furthermore, 37.25 ps root-mean-square (RMS) is measured for the proposed MPDL-TDC inputting a constant delay source. Therefore, the proposed MPDL-TDC is recommended to implement in FPGA-based TDC achieving a high-resolution time and linearity performance.

A high-density, 129-channel time-to-digital converter in FPGA for trigger-less data acquisition systems

Design of time interval generator based on hybrid counting method

Time-to-digital-converter based on multiple-tapped-delay-line

We present the implementation of a high-resolution Time-to-Digital Converter (TDC) in a Field Programmable Gate Array (FPGA) from Xilinx Virtex-5 family. The design of the TDC is based on a counter and interpolator method. Dedicated carry-in lines in CARRY4 blocks of the Virtex-5 FPGA are utilized for time interpolation, which realizes the fine time measurement within a system clock period. Simulation results show that the delay from CIN to COUT in CARRY4 block is as large as 104 ps. Thus we subdivide the delay cell into finer taps for a higher resolution. Considering the inhomogeneous delay cells, multiple strategies are applied to perform the calibration and to enhance the TDC resolution. Meanwhile, we also apply Place and Route (PAR) constraints to fit our TDC requirements. Finally, a total of 16 TDC channels with a timing performance of about 15 ps RMS are implemented in one FPGA.

A cost-effective field-programmable-gate-array-based pulse processor for biomedical imaging applications

This article presents a low-power highly linear multichannel data acquisition (DAQ) system for silicon photomultiplier (SiPM) readout. A low-input impedance current-mode front-end with a programmable current gain is developed to achieve high-precision charge readout over a large dynamic range. An integrated 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) shared by 16 readout channels in a time-multiplexed manner is designed to reduce the overall chip area and power consumption of the SiPM readout. Implementation challenges of field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) including bubble error, zero length bins, interclock region nonlinearity, and chain overflow, are addressed for high accuracy timing measurement. Multichain averaging is developed to improve the TDC linearity. Fabricated in a 180-nm CMOS process, the current-mode 16-channel readout application-specific integrated circuit (ASIC) achieves 3.6% maximum gain nonlinearity over an input dynamic range of 800 pC with dissipating 3.89 mW of power per readout channel, and the ADC achieves an SFDR of 58.34 dB and an SNDR of 51.37 dB at 16 MS/s. Implemented in a Xilinx 28-nm Kintex-7 FPGA, the 32-channel TDC achieves a 15-ps root mean square (RMS) resolution, a differential nonlinearity (DNL) of less than 4 ps, and an integral nonlinearity (INL) of less than 10 ps.

The tapped delay line in FPGAs has been widely used as a core component for constructing highprecision Time-to-Digital Converters (TDCs). Due to its inherent asymmetry, the delay cell introduces different propagation delays for rising and falling edges. The stability of this difference has been characterized using the Xilinx VM1402 FPGA. Based on these findings, a novel method has been proposed to implement a low-deadtime, pulse-shrinking TDC using the delay chain. This design supports both edge time and pulse width measurements. The proposed architecture determines the point at which a pulse injected into the chain disappears, allowing the pulse width to be calculated using pre-measured latency parameters. Code density tests show that the TDC achieves a resolution of approximately 1.57 ps, with corresponding DNL of -0.97 LSB to 5.42 LSB. Due to jitter accumulation along the pulse propagation path, the measurement precision degrades from 0.83 ps to 9.04 ps as the injected pulse width increases from 0 to 6 ns. To improve this, a module supporting pulse width shortening is introduced, enhancing the measurement precision to better than 6 ps. Temperature stability measurements show that the LSB exhibits a temperature coefficient of approximately 0.13 % per degree Celsius. This paper presents the design details of the TDC, the results of edge time and pulse width measurements, and the efforts to improve system precision through multiple times of measurements for individual event.

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.

High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

Among numerous time-to-digital converters (TDC), tapped delay line (TDL) is the most commonly used architecture. However, its dead time of more than two cycles is inefficient for applications with high measurement rates. Limited by the device process, the delay of each cell in the TDL exhibits a random and uneven distribution, degrading the linearity of the TDC. In this study, a dual-edge TDL structure is proposed. By improving original pulse-holding circuit, the propagated signal injected into the fine measurement chain is alternately switched between rising and falling edge signals to decrease the dead time to one cycle. The nonlinearity problem is alleviated by an enhanced tapped sampling sequence circuit. A dual-edge “1” count encoder is introduced to effectively simplify the difficulty of addressing the bubble problem. Bit-by-bit calibration and a moving average filter are adopted to improve accuracy. The proposed scheme has been verified on a Xilinx Kintex-7 FPGA platform. The resolution (least significant bit, LSB1) is 12.07 ps when the propagated signal in the TDL is the rising edge. The differential nonlinearity (DNL) is [-0.81,0.93] LSB1, and the integral nonlinearity (INL) is between [-2.33,2.19] LSB1. At the falling edge, the resolution (LSB0) is 11.90 ps, between [-0.73,0.98] LSB0 and [-2.46,1.83] LSB0 for DNL and INL, respectively. In addition, the accuracy reaches 15.25 ps after multiple measurements for different time intervals separately.

A new Vernier-type time-to-digital converter (TDC) with low resource consumption and medium performance is designed and evaluated in a Xilinx Kintex-7 field programmable gate array (FPGA). The converter requires only one ring oscillator, and its resolution is the period difference between two signals of the oscillation pulse and system clock. The conversion is finished by judging the alignment between the oscillation pulse with either the rising edge or the falling edge of the system clock. The difficulty of this new method is the design of the ring oscillator, which is required to oscillate with a frequency closing to the system clock frequency in any position of FPGA to keep TDC performance less position-dependent. The design of such a ring oscillator is proposed and 28 identical TDCs are implemented in 14 clock regions of the FPGA for performance evaluation. Through the TDC bin width measurement, the average resolution of 28 TDCs is 61.1 ps and the variation of resolution over location is 31.5 ps. Through time-interval measurement, the average time-interval RMS precision in 14 clock regions is 28.9 ps and the corresponding precision variation over location is 8.7 ps. The test results show that the proposed TDC is applicable, in particular to cases that multi-channel capability with medium performance is highly required.