High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

SOI device is promised to be a mobile and wireless network applications as it has better potential of high speed, low operating voltage and Q-factor. Gate Body directly connected SOI MOSFET suppresses Sees historical effects and is promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

A design methodology for sequential logic circuits using controllable flip-flops is proposed. The flip-flop setup time and propagation delay is controlled with a process, voltage and temperature (PVT) detector using an additional setup time and delay control (SDC) input. With this SDC enable, it is possible to enhance the circuit timing performance when PVT variations are detected. The PVT detector is based in the propagation delay of digital buffers. When an increase in the propagation delay is detected in the digital logic, the SDC flip-flop input is enabled to reduce its setup time and Clk-Q propagation delay. When the PVT conditions are maintained under the selected threshold, the SDC control remains disabled, saving power. The proposed flip-flop and PVT detector are designed and characterized in a TSMC 28 nm bulk CMOS technology.

This paper presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 4 ps, fabricated in a 65 nm Complementary Metal Oxide Semiconductor (CMOS) technology. To achieve the low resolution, the delay elements are implemented using a new interlocked interpolation technique to reduce the Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) error. The delay line is placed inside a Delay Locked Look (DLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation.

This study proposes a high-resolution short time interval measurement system based on the Vernier delay line (VDL) method. It should be noted that the programmable delay elements (PDEs) in the Xilinx field programmable gate arrays (FPGAs) provide a novel realization of delay lines. The delay lines can provide an accurate delay difference of 50 ps, which is process, voltage and temperature (PVT) invariant. An excellent consistency for the delay lines can be achieved by adjusting the timing and layout to minimize the measurement errors. The resolution achieved was 58 ps. Experimental results indicate a measurement standard deviation of 36 ps, a differential nonlinearity (DNL) of 36 ps and integral nonlinearity (INL) of 14 ps. The system features high accuracy, easy implementation and low cost.

This paper presents the design and implementation of a new digital-to-time converter (DTC). The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs) to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA) chip.

The existing state of the art lock/out-of-lock detection schemes used in PLL (Phase lock loop) suffers from process, voltage and temperature (PVT) variations and has limited accuracy especially in fractional PLL mode of operation. Moreover, the schemes are not suitable to detect both lock and out-of-lock condition accurately. This paper describes a novel mixed signal scheme which incorporates detection of both lock and out-of-lock conditions of a PLL. The scheme covers integer and fractional PLL modes of operations and programmable to generate lock condition to a very high accuracy. Furthermore, this digital detection scheme is not prone to process, voltage and temperature variations.

The principle of tapped-delay line (TDL) style field programmable gate array (FPGA)-based time-to-digital converters (TDC) requires finer delay granularity for higher time resolution. Given a tapped delay line constructed with carry chains in an FPGA, it is desirable to find a solution subdividing the intrinsic delay elements further, so that the TDC can achieve a time resolution beyond its cell delay. In this paper, after exploring the available logic resource in Xilinx Kintex UltraScale FPGA, we propose a dual-sampling method to have the TDL status sampled twice. The effect of the new method is equivalent to double the number of taps in the delay line, therefore a significant improvement in time resolution should present. Two TDC channels have been implemented in a Kintex UltraScale FPGA and the effectiveness of the new method is investigated. For fixed time intervals in the range from 0 to 440 ns, the average time resolutions measured by the two TDC channels are respectively 3.9 ps with the dual-sampling method and 5.8 ps by the conventional single-sampling method. In addition, the TDC design maintains advantages of multichannel capability and high measurement throughput in our previous design. Every part of TDC, including dual-sampling, code conversion and on-line calibration could run at 500 MHz clock frequency.

In this paper, we proposed a Ring Time-to-Digital Converter (RTDC)-based Capacitance-to-Digital Converter (CDC) that is insensitive to PVT variation. The proposed CDC embeds a Capacitance-to-Time Converter (C2T) with high linearity, leveraging a parasitic elimination technique to counteract environment changes. Thanks to the ring structure of RTDC, the presented CDC has theoretically infinite detection range. However, RTDC suffers from the process, voltage and temperature (PVT) variation, compromising its dynamic range. This paper proposed a new architecture that matches the current sources of the front-end and delay cells in the RTDC. Therefore, the front-end and RTDC have the same PVT response, leading to an inherent-PVT-stabilized feature. The proposed CDC was implemented in a 40-nm LP CMOS process. Simulation results show that it achieves 0.55fF resolution under 10pF parasitic capacitance and it covers 3.75-64pF capacitance detection range, with a 0.56pJ/conversion-step figure of merit and a maximum 20us conversion time.

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

For high system performance in VLSI chips dynamic CMOS logic circuit techniques are used. As continue scaling down the dimension of transistors parameter variation becomes a serious issue in very deep sub-micron regime. The overall performance of any logic circuit reduces by increasing leakage current and variability of parameters in scaled device. To overcome the variability issue in sub-micron regime the design must be aware of variations. In this paper DOIND logic approach is proposed for domino logic to analyze the variability issue. This approach reduces leakage current as well as it reduces the variability issue with minimum delay penalty. Various process, voltage and temperature (PVT) variations are analyzed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation result shows that DOIND approach has less affect of PVT variations as compare to domino logic circuit.

A new approach for pipeline time-to-digital converters (TDCs) is introduced in this paper. The analog interpolation and voltage amplification methods for digitalizing the time intervals between the rising edges of two input signals are employed in the recommended converter. It consists of four 2.5b/stage time-to-digital converters and three voltage amplifiers (VAs) and will be a 9-bit pipeline TDC. Besides, a new VA is suggested in this paper. The delay cells such as delay line TDCs and vernier delay line TDCs (VDL–TDCs) are not used in this converter. Moreover, a triple-slope conversion is achieved by performing of the interpolation. Lots of advantages can be mentioned for the proposed converter such as; lower complexity, lower temperature sensitivity, power supply and process (PVT) variations, and higher accuracy in comparison with the time-to-digital converters which have been proposed previously. Furthermore, the differential non linearity (DNL) and the integral non linearity (INL) errors are decreased while the dynamic range, the time resolution, and the linear range of the TDC are developed significantly. The simulation results for INL and DNL in the proposed TDC are 0.83 LSB and 0.92 LSB, correspondingly. In addition, the time resolution is improved to 0.234 ps. To verify the validity of theoretical analysis, designing and simulation of the TDC is done in TSMC 45 nm CMOS technology. The comparison between the theoretical analysis and simulation results approves the superiorities and characteristics of the proposed TDC.

In this paper, a PVT (process, voltage and temperature)-insensitive Ka-Band Class-D VCO with average current control in 65 nm CMOS process is presented. The proposed VCO is based on a Class-D VCO architecture to achieve good noise performance and low power consumption. Different from the traditional structure, a tail current source is added to control the average operation current of the VCO. This structure can achieve a stable VCO performance against PVT variations. And the output phase noise of the VCO is immune to the noise and ripples on the external power supply owing to the power supply rejection characteristic of the current source. Moreover, a typical internal power supply circuit is introduced and a minor improvement is addressed to realize the current source without deteriorating the total VCO phase noise. Quantitative analysis and simulation indicate that the proposed structure removes the strict requirements to the power supply circuits comparing to the traditional scheme. The experimental results show that at the frequency of 34.5 GHz, the phase noise of the proposed VCO is - 98 dBc/Hz at 1 MHz offset with the power supply circuit, the core power is 1.7 mW, and the core area is 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

This paper proposes a new design technique of a stable, low input impedance, high sensitivity, high gain and low-power Potentiostat using carbon nanotube FETs (CNTFETs) at 32 nm level that utilizes different input voltages for verifying voltage follower performance. The fully differential architecture suppresses the common mode interference. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.

We present the implementation of a high-resolution Time-to-Digital Converter (TDC) in a Field Programmable Gate Array (FPGA) from Xilinx Virtex-5 family. The design of the TDC is based on a counter and interpolator method. Dedicated carry-in lines in CARRY4 blocks of the Virtex-5 FPGA are utilized for time interpolation, which realizes the fine time measurement within a system clock period. Simulation results show that the delay from CIN to COUT in CARRY4 block is as large as 104 ps. Thus we subdivide the delay cell into finer taps for a higher resolution. Considering the inhomogeneous delay cells, multiple strategies are applied to perform the calibration and to enhance the TDC resolution. Meanwhile, we also apply Place and Route (PAR) constraints to fit our TDC requirements. Finally, a total of 16 TDC channels with a timing performance of about 15 ps RMS are implemented in one FPGA.

This article presents a low-power highly linear multichannel data acquisition (DAQ) system for silicon photomultiplier (SiPM) readout. A low-input impedance current-mode front-end with a programmable current gain is developed to achieve high-precision charge readout over a large dynamic range. An integrated 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) shared by 16 readout channels in a time-multiplexed manner is designed to reduce the overall chip area and power consumption of the SiPM readout. Implementation challenges of field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) including bubble error, zero length bins, interclock region nonlinearity, and chain overflow, are addressed for high accuracy timing measurement. Multichain averaging is developed to improve the TDC linearity. Fabricated in a 180-nm CMOS process, the current-mode 16-channel readout application-specific integrated circuit (ASIC) achieves 3.6% maximum gain nonlinearity over an input dynamic range of 800 pC with dissipating 3.89 mW of power per readout channel, and the ADC achieves an SFDR of 58.34 dB and an SNDR of 51.37 dB at 16 MS/s. Implemented in a Xilinx 28-nm Kintex-7 FPGA, the 32-channel TDC achieves a 15-ps root mean square (RMS) resolution, a differential nonlinearity (DNL) of less than 4 ps, and an integral nonlinearity (INL) of less than 10 ps.