A design methodology using flip-flops controlled by PVT variation detection

SOI device is promised to be a mobile and wireless network applications as it has better potential of high speed, low operating voltage and Q-factor. Gate Body directly connected SOI MOSFET suppresses Sees historical effects and is promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

For high system performance in VLSI chips dynamic CMOS logic circuit techniques are used. As continue scaling down the dimension of transistors parameter variation becomes a serious issue in very deep sub-micron regime. The overall performance of any logic circuit reduces by increasing leakage current and variability of parameters in scaled device. To overcome the variability issue in sub-micron regime the design must be aware of variations. In this paper DOIND logic approach is proposed for domino logic to analyze the variability issue. This approach reduces leakage current as well as it reduces the variability issue with minimum delay penalty. Various process, voltage and temperature (PVT) variations are analyzed at 70 nm technology node for a domino logic and DOIND logic buffer using tanner EDA tool. Simulation result shows that DOIND approach has less affect of PVT variations as compare to domino logic circuit.

In this paper, a PVT (process, voltage and temperature)-insensitive Ka-Band Class-D VCO with average current control in 65 nm CMOS process is presented. The proposed VCO is based on a Class-D VCO architecture to achieve good noise performance and low power consumption. Different from the traditional structure, a tail current source is added to control the average operation current of the VCO. This structure can achieve a stable VCO performance against PVT variations. And the output phase noise of the VCO is immune to the noise and ripples on the external power supply owing to the power supply rejection characteristic of the current source. Moreover, a typical internal power supply circuit is introduced and a minor improvement is addressed to realize the current source without deteriorating the total VCO phase noise. Quantitative analysis and simulation indicate that the proposed structure removes the strict requirements to the power supply circuits comparing to the traditional scheme. The experimental results show that at the frequency of 34.5 GHz, the phase noise of the proposed VCO is - 98 dBc/Hz at 1 MHz offset with the power supply circuit, the core power is 1.7 mW, and the core area is 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A high linear high speed low distortion current squarer/divider circuit is proposed in this paper. The presented circuit is based on floating-gate MOS translinear (FGMTL) principle in saturation region and consists of a dual translinear loop. The designed circuit is simulated by HSPICE simulator in TSMC 0.18 μm (level-49 parameters) CMOS technology. Simulation results of the current squarer circuit with 1-V DC supply voltage show that the maximum nonlinearity as 0.75%, the -3dB bandwidth as 1.15 GHz, the total harmonic distortion (THD) as 0.25% (at 1 MHz), the maximum and static power consumption are 82 μW and 20.5 μW, respectively. Monte Carlo simulations are also performed that prove their superiority over some other art works and robustness against PVT (process, voltage and temperature) variations.

In addition to the conventional PVT (Process, Voltage and Temperature) variation, time-dependent current fluctuation such as random telegraph noise (RTN) poses a new challenge on VLSI reliability. In this paper, we show that compared with the static random variation, RTN amplitude of a particular device is not constant across supply voltages and temperatures. A device may show large RTN amplitude at one operating condition and small amplitude at another operating condition. As a result, RTN amplitude distribution becomes uncorrelated across a wide range of voltage and temperature. The emergence of uncorrelated distribution causes significant degradation of worst-case values. Analysis results based on variability models from a 65 nm silicon-on-insulator process show that uncorrelated RTN degrades the worst-case threshold voltage value significantly compared with that where RTN is not considered. Delay variation analysis shows that consideration of RTN in the statistical analysis have little impact at high supply voltage. However, at low voltage operation, RTN can degrade the worst-case value by more than 5 %.

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

This paper proposes a new design technique of a stable, low input impedance, high sensitivity, high gain and low-power Potentiostat using carbon nanotube FETs (CNTFETs) at 32 nm level that utilizes different input voltages for verifying voltage follower performance. The fully differential architecture suppresses the common mode interference. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.

In this paper, we proposed a Ring Time-to-Digital Converter (RTDC)-based Capacitance-to-Digital Converter (CDC) that is insensitive to PVT variation. The proposed CDC embeds a Capacitance-to-Time Converter (C2T) with high linearity, leveraging a parasitic elimination technique to counteract environment changes. Thanks to the ring structure of RTDC, the presented CDC has theoretically infinite detection range. However, RTDC suffers from the process, voltage and temperature (PVT) variation, compromising its dynamic range. This paper proposed a new architecture that matches the current sources of the front-end and delay cells in the RTDC. Therefore, the front-end and RTDC have the same PVT response, leading to an inherent-PVT-stabilized feature. The proposed CDC was implemented in a 40-nm LP CMOS process. Simulation results show that it achieves 0.55fF resolution under 10pF parasitic capacitance and it covers 3.75-64pF capacitance detection range, with a 0.56pJ/conversion-step figure of merit and a maximum 20us conversion time.

This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7[Formula: see text]nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation [Formula: see text] for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation [Formula: see text] for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry’s production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies.

With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of power-aware design methodologies have resulted in potentially significant variations in power consumption under different process, voltage and temperature (PVT) corners. In this paper, we first investigate the impact of PVT corners on power consumption at the System-on-Chip (SoC) level, especially for the on-chip communication infrastructure. Given a target technology library, we then show how it is possible to scale up and abstract the PVT variability at the system level, allowing characterization of the PVT-aware design space early in the design flow. We conducted several experiments to estimate power for PVT corner cases, at the gate-level, as well as at the higher system-level. Our preliminary results are very interesting and indicate that: (i) there are significant variations in power consumption across PVT corners, and (ii) the PVT-aware power estimation problem may be amenable to a reasonably simple abstraction at the system-level.

In the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of non-scalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Fin-shaped field effect transistor (FinFET) is an important device which uses the concept of multi-gates and it is not only scalable but also dissipate lower power at lower technology nodes. This paper designs a low leakage input dependent (INDEP) approach for FinFET devices at 16 nm technology node. Numbers of logic gates are designed and simulated with the help of MOSFET and FinFET devices. Simulation results are compared by calculating the important parameters like leakage power, delay and power delay product (PDP). The designed low leakage INDEP approach is compared with the leakage control transistor (LECTOR) technique. Simulation results for different logic circuits show the large reduction in leakage power in case of FinFET logic gates as compared to MOSFET devices and more leakage saving in case of INDEP approach as compared to conventional as well as LECTOR technique. Reliability in terms of process, voltage and temperature (PVT) variations is checked by running the Monte-Carlo simulations for 1000 samples and observed that INDEP circuits are more reliable.

This paper presents a design methodology for ultra-low voltage (ULV) analog integrated circuits. This methodology is based on an optimization process using Simulated Annealing (SA) heuristic and electrical simulations. The SA algorithm explores the design space to obtain design feasible solutions at the same time that the effects of process, voltage and temperature (PVT) variations are analyzed with corners simulations. A low-pass filter was designed in the TSMC 130 nm process using the proposed methodology. The results show a 0.5–0.6 V active filter with 2.47 MHz cut-off frequency and power dissipation of 640 µW, in according with the IEEE 802.15.4 standard for 2.5 GHz low power receivers.

In this paper, we present a novel robust sliding-mode controller for stabilizing supply voltage and clock frequency of dual core processors determined by dynamic voltage and frequency scaling (DVFS) methods in the presence of systematic and random variations. We show that maximum rejection for process, voltage and temperature (PVT) variations can be achieved by using the proposed sliding-mode controller. The stabilization of the presented controller is confirmed by the Lyapanov method. Experimental results demonstrate maximum 20% robustness against 20% parameter variations for a hardware of two core processors executing a JPEG decoding application.

One of the major requirements for testing VLSI devices is the validation of its timing specifications. Timing specifications would typically include frequency, propagation delays, minimum pulse width, phase offsets, setup time and hold time measurements. Although parametric specifications may exist for a nominal speed (frequency) of operation of the digital device, it may be necessary to characterize the device under test (DUT) to determine the highest operating frequency of the DUT and the required environmental parameters to run at the highest frequency. Characterization involves measurement of setup time, hold time and pulse width of the signals. In this paper, we have presented an automated AC (timing) characterization flow for digital circuit testing. We have recommended a STIL (Standard Tester Interface Language) like syntax for the timing tests. Various timing data (setup and hold time, propagation delay etc.) are measured in the first pass of the characterization process and are automatically back annotated to the timing test flow to reduce the total test cycle time. The approach will also help in finding the maximum operating frequency of the DUT and speed binning (i.e., sorting the devices based on their operating frequency).