An optimization-based design methodology with PVT analysis for ultra-low voltage analog ICs

SOI device is promised to be a mobile and wireless network applications as it has better potential of high speed, low operating voltage and Q-factor. Gate Body directly connected SOI MOSFET suppresses Sees historical effects and is promised technologies that let the logic circuitry work in ultra low voltage. Compared to Bulk-Si MOSFET, GBSOI can reduce its power supply voltage by 30%, its current by 26% and its power dissipation by 47%. However sub-Gbps level clocking circuits with ultra low voltage require the smaller PVT (process, voltage and temperature) variation. This paper presents an architecture to stabilize SOI logic circuitry against PVT variation especially under ultra low power supply voltage. Deviation of gate delay caused by PVT variation is reduced to 1.6%, while 40% with Bulk-Si. This system realizes the cell libraries whose gate delay is constant despite PVT variation. They greatly help designing circuitry especially under ultra low voltage.

A design methodology for sequential logic circuits using controllable flip-flops is proposed. The flip-flop setup time and propagation delay is controlled with a process, voltage and temperature (PVT) detector using an additional setup time and delay control (SDC) input. With this SDC enable, it is possible to enhance the circuit timing performance when PVT variations are detected. The PVT detector is based in the propagation delay of digital buffers. When an increase in the propagation delay is detected in the digital logic, the SDC flip-flop input is enabled to reduce its setup time and Clk-Q propagation delay. When the PVT conditions are maintained under the selected threshold, the SDC control remains disabled, saving power. The proposed flip-flop and PVT detector are designed and characterized in a TSMC 28 nm bulk CMOS technology.

We apply the output prediction logic (OPL) technique to the differential CMOS logic family. Including the effects of process, voltage and temperature (PVT) variations, we show that OPL differential CMOS is more than 40% faster than the single-rail OPL-dynamic logic family, and nearly 5 times faster than optimized static CMOS. We also demonstrate an OPL-differential 64:2 compressor that is 37% faster than the OPL-dynamic version. Finally, we show that OPL-differential is nearly twice as fast as differential domino.

Most neural signal monitoring front-ends rely on the low-pass filter (LPF) to filter out the out-of-band interference and noise. A large time constant is required for such filters due to the low-frequency characteristic of neural signals. MOSFETs operating in the sub-threshold region (pseudo resistors) are widely used as resistors due to their large impedance with a small die area, which shows the potential to realize a considerable time constant LPF with acceptable capacitors. However, its linearity and impedance are limited by the applied voltage and suffer from process, voltage and temperature (PVT) variations. In this work, a subthreshold-source-follower (SSF) based LPF with self-biased pseudo-resistors (PRs) is presented. The self-biased scheme for PRs substantially increases the linearity and impedance without extra area consumption and results in a tunable low cut-off frequency. The proposed circuit is designed and simulated in the TSMC 40-nm CMOS process. Simulation results show that it can achieve a DC gain of 0 dB, an input-referred noise (IRN) of 44 µV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</inf> , a THD@1 Hz of 0.49%, a die area of 0.008 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a low cut-off frequency of 82 Hz while the power consumption is 16.1 nW. Performances achieved are comparable with the state of the art.

This paper describes a novel complementary metal oxide semiconductor (CMOS) bootstrapped driver circuit for driving large resistive capacitive (RC) loads. The proposed bootstrapped driver reduces the leakage as well as process, voltage and temperature (PVT) variations from the boosted nodes with higher switching speed. Very large scale integration (VLSI) designers need boosted output for the logic circuits which are operating in ultra-deep submicron regime under widespread use of low voltage. Proposed CMOS bootstrapped driver circuit is easy in design; built with minimum number of transistors and have high boosting efficiency with sharp output performance. Comparative evaluations with existing bootstrapped driver circuits are reported. Simulation results are derived by HSPICE tool with predictive technology model (PTM) bulk CMOS process fabrication at 32 nm technology node. The ability of large leakage reduction makes this driver superior as compared to active drivers. An average of 96.97% leakage current is saved at nominal ultra-low voltage of 0.15 V. Monte-Carlo analysis indicates that the proposed bootstrapped driver has less sensitivity of PVT variations. The power consumption and delay sensitivities are reduced by 10 × and 4.12 × as compared to conventional circuit.

With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of power-aware design methodologies have resulted in potentially significant variations in power consumption under different process, voltage and temperature (PVT) corners. In this paper, we first investigate the impact of PVT corners on power consumption at the System-on-Chip (SoC) level, especially for the on-chip communication infrastructure. Given a target technology library, we then show how it is possible to scale up and abstract the PVT variability at the system level, allowing characterization of the PVT-aware design space early in the design flow. We conducted several experiments to estimate power for PVT corner cases, at the gate-level, as well as at the higher system-level. Our preliminary results are very interesting and indicate that: (i) there are significant variations in power consumption across PVT corners, and (ii) the PVT-aware power estimation problem may be amenable to a reasonably simple abstraction at the system-level.

This research work focuses on implementation of the FinFET-based complementary metal-oxide-semiconductor (CMOS) Full Adder circuits for different transistor configurations using ASAP7 FinFET model. First, this work examines FinFET-based AND-OR-invert (AOI) gates using different topologies, and second, a FinFET-based CMOS Full Adder circuit at the 7[Formula: see text]nm technology node is analyzed with respect to its process, voltage and temperature (PVT) variability effect measured in terms of the normalized standard deviation of different performance metrics. The comparison is made between conventional (CFFA1) and proposed (FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8) FinFET-based CMOS full adder circuits. The aim is to determine the optimal design configuration of the FinFET full adder circuit with the minimum impact of PVT variability. On examining the power delay product (PDP) variability, it is found that variations in FFA2, FFA3, FFA4, FFA5, FFA6, FFA7 and FFA8 are significantly lower than CFFA1 by 6.30%, 4.68%, 10.30%, 65.48%, 68.05%, 65.61% and 17.20%, respectively. Among all the proposed configurations, normalized standard deviation [Formula: see text] for the PDP metric is lowest in FFA6, followed by FFA7, FFA5, FFA8, FFA4, FFA2 and FFA3. The normalized standard deviation [Formula: see text] for power dissipation, however, is lowest in FFA8. In addition, a layout comparison analysis of conventional and proposed full adder circuits reveals that FFA7 has the least area, followed by FFA8, FFA6, FFA5, FFA3, FFA4, FFA2 and CFFA1. The area of FFA2, FFA3, FFA4, FFA5 and FFA6 has decreased by 3.29%, 3.51%, 3.50%, 5.14% and 5.52%, while FFA7 and FFA8 have experienced a decrease in area by 13.87% and 14.36%, respectively, as compared to conventional CFFA1. The proposed layout of FinFET-based CMOS Full Adders can be directly transferred into the foundry’s production line for manufacturing purposes. The overall investigation led us to conclude that FFA8 is the most efficient of all due to the lowest power variation, lower delay variation and lower PDP variation, moreover it has a reduced layout area among all the discussed designs. However, there is a tradeoff in terms of penalty in nominal power, propagation delay and PDP in the proposed topologies.

SUMMARY This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 μm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closedloop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/ √ Hz, current consumption of 14 μA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter’s building block for low power design. The filter’s single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signalto-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 μW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 μm CMOS process.

Photoacoustic (PA) imaging and sensing based on optical excitation and acoustic detection are emerging recently. The main issue of the PA systems is the poor SNR at the output of the sensors. The power consumption and size of the receiver are also crucial for the systems. Thus, several techniques are proposed in the analog front-end (AFE) and the analog-to-digital convertor (ADC) to improve the output SNR and power efficiency of the receiver. A resonant noise matching (RNM) technique is proposed to improve the sensitivity of ultrasound transducers. Diverse from the power matching which aims to maximize the output power from transducer in conventional electrical impedance matching (EIM) technique, the RNM maximizes the output voltage. The advantage of RNM is that it can also equivalently reduce the LNA’s input-referred noise and thus minimize the noise figure (NF) of the ultrasound receiver. Measurement results show that, the output signal is improved by 5 times through the proposed RNM technique, which is 66.7% larger than that of conventional methods. In addition, the sensitivity of the receiver is significantly improved by more than 10.4 dB which is beneficial for a variety of applications of piezoelectric ultrasound transducers. Thereafter, a high sensitivity and high dynamic range AFE is developed and fabricated in TSMC 65 nm CMOS process. An LNA with 30 dB gain and low input-referred noise (1 nV/Hz) is designed to amplify the input signal and suppress the noise from subsequent stages. Then a 3rd order Butterworth low-pass filter (LPF) with 5-20 MHz cut-off frequency is connected behind the LNA to reduce the out-of-band noise. Finally, a variable gain amplifier (VGA) which covers a gain range 0-45 dB with 20 MHz bandwidth are implemented in the AFE. The AFE is also applied in a photoacoustic sensor system which can achieve coherent lock-in function to detect weak PA signals noninvasively at in-vivo environments. An asynchronous SAR ADC with a novel mismatch error shaping (MES) technique is designed and fabricated. The power dissipation of the SAR ADC is dominated by the comparator, DAC and digital logic circuits. To reduce digital power consumption, the asynchronous timing sequence is adopted. As known, the resolution of SAR ADC is limited by the non-linearity of DAC and noise of comparator. The linearity of the DAC can be efficiently improved by the MES technique. The proposed novel MES technique can remove the flash ADC and DWA digital circuits in the convention MES technique, and thus improve the power efficiency. Noise shaping technique is also applied in the SAR ADC to reduce the comparator noise and improve the output SNR. In addition, another MES technique based on a double input range SAR ADC is also proposed. Through this method, the input signal is not necessary to be reduced by 2 times, which happens in the first proposed MES. Consequently, the output SNR can be improved by 3 dB. Overall, the main contributions of the thesis are: a) the RNM technique which is designed to improve the sensor’s sensitivity, b) A 0.18µVrms super-sensitivity photoacoustic imager based on coherent detection for deep in-vivo imaging and c) a low power and high-resolution SAR ADC with improved MES technique.

In this work, an ultra low voltage, second order low pass active-RC filter is designed in 90 nm CMOS process. A bulk-driven transconductor and a feed-forward compensated operational transconductance amplifier (OTA) are used as building blocks of the filter. Operating with a supply voltage of 0.5 V, filter exhibits a low pass Butterworth response with a cutoff frequency of 1 MHz. A mathematical model of the filter is developed using descriptor state-space equations for optimizing the filter response. The designed filter consumes a power as less as 91.99 μW with a figure of merit (FoM) of 3.39 fJ/pole.

Some harsh environments, such as those encountered by aerospace vehicles and various types of industrial machinery, contain high frequency/amplitude mechanical vibrations. Unfortunately, some very useful components are sensitive to these high frequency mechanical vibrations. Examples include MEMS gyroscopes and resonators, oscillators and some micro optics. Exposure of these components to high frequency mechanical vibrations present in the operating environment can result in problems ranging from an increased noise floor to component failure. Passive micromachined silicon lowpass filter structures (spring-mass-damper) have been demonstrated in recent years. However, the performance of these filter structures is typically limited by low damping (especially if operated in near-vacuum environments) and a lack of tunability after fabrication. Active filter topologies, such as piezoelectric, electrostrictive-polymer-film and SMA have also been investigated in recent years. Electrostatic actuators, however, are utilized in many micromachined silicon devices to generate mechanical motion. They offer a number of advantages, including low power, fast response time, compatibility with silicon micromachining, capacitive position measurement and relative simplicity of fabrication. This paper presents an approach for realizing active micromachined mechanical lowpass vibration isolation filters by integrating an electrostatic actuator with the micromachined passive filter structure to realize an active mechanical lowpass filter. Although the electrostatic actuator can be used to adjust the filter resonant frequency, the primary application is for increasing the damping to an acceptable level. The physical size of these active filters is suitable for use in or as packaging for sensitive electronic and MEMS devices, such as MEMS vibratory gyroscope chips.

This paper presents a design methodology for the simultaneous optimization of jitter and power consumption in ultra-low jitter clock recovery circuits ( rms ) for high-performance ADCs. The key idea is twofold: a) a smart parameterization of transistor sizes to have smooth dependence of specifications on the design variables, b) performing a design space sub-sampling which allows capturing the whole circuit performance for reducing computation resources and time during optimization. The proposed methodology, which can easily incorporate process voltage and temperature (PVT) variations, has been used to perform a systematic design space exploration that provides sub-100fs jitter clock recovery circuits in two CMOS commercial processes at different technological nodes (1.8V 0.18µm and 1.2V 90nm).

This paper presents a 4th order continuous-time low-power reconfigurable low pass filter (LPF) using active-Gm-RC structure for multi-mode multi-standard communications. Programmable OTAs (operational transconductor amplifier) and R-C arrays are employed to realize the reconfiguration of cut-off frequencies, power consumption, and linearity of the LPF. Designed and fabricated in 0.18 μm CMOS technology, the proposed LPF achieves a measured reconfigurable cut-off frequency from 1.39 to 10.6 MHz with the consumed power from 0.45 to 1.35 mW. The measured dc gain is 17.3 dB and the 1-dB compression point is -9.7 dBVpp. The proposed LPF occupied an area of 0.64 mm2 including testing pads.

Although electrical simulation has become a vital tool in the design process of memory devices, memory testing has not yet been able to employ electrical simulation as an integral part of the test generation and optimization process. This is due to the exponential complexity of the simulation-based fault analysis, a complexity that made such an analysis impractical. This paper describes new methods to reduce the complexity of the fault analysis from exponential to constant with respect to the number of analyzed operations, thereby making it possible: 1) to use electrical simulation to generate test patterns; and 2) to perform simulation-based stress optimization of tests. The paper also discusses ways to analyze the impact of idle time on the faulty behavior. In addition, results of a fault analysis study performed to verify the new analysis method are shown, where the new analysis reduces the analysis time by a factor of 30.

Crude oil distillation is one of the most economical separation processes in the petroleum refinery industry. In this work, a novel optimization-based design methodology, termed as Surrogates Aided Constrained Optimization Design (SACOD), is proposed for time-consuming objectives and constraints in the evolutionary optimization design of Crude oil Distillation Units (CDUs). By constructing global and local surrogate column models of the CDUs to maximize economic profits, a constraint-handling optimizer is used for infilling operations and optimization search. The framework of SACOD consists of Surrogate Models Construction, Model Management, and Particle Swarm Optimization (PSO) Mixed-Integer Constrained Evolutionary (PSO-MICE) search. The optimization results of the CDUs indicate that SACOD outperforms the single surrogate column model based approaches. Besides, the results of the proposed method are more consistent with that of the rigorous CDU model optimization approach, whereas the evaluation numbers of the time-consuming rigorous models can be significantly reduced.